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| ht46ru66/ht46cu66 a/d type 8-bit mcu with lcd rev. 1.30 1 may 25, 2011 features operating voltage: f sys =4mhz: 2.2v~5.5v f sys =8mhz: 3.3v~5.5v 32 bidirectional i/o lines two external interrupt inputs two 16-bit programmable timer/event counters with programmable frequency divider, pfd, function one 8-bit programmable timer/event counter with source clock prescaler 47 3or46 4 segment lcd driver with logic output option for seg0~seg23) 16k 16 program memory 576 8 data memory ram universal asynchronous receiver transmitter (uart) pfd function for sound generation real time clock - rtc 8-bit rtc prescaler watchdog timer buzzer output function crystal, rc and 32768hz crystal system oscillator option power down and wake-up functions reduce power consumption 16-level subroutine nesting 8-channel 12-bit resolution a/d converter 4-channel pwm output shared with 4 i/o lines bit manipulation instruction 16-bit table read instruction up to 0.5 s instruction cycle with 8mhz system clock 63 powerful instructions instruction execution within 1 or 2 machine cycles low voltage reset/detector function 52-pin qfp, 56-pin ssop, 100-pin lqfp packages general description the ht46ru66/ht46cu66 are 8-bit, high perfor - mance, risc architecture microcontroller devices spe - cifically designed for a/d product applications that interface directly to analog signals and which require an lcd interface. the ht46cu66 mask version device, is fully pin and functionally compatible with its sister ht46ru66 otp device. the advantages of low power consumption, i/o flexibility, timer functions, oscillator options, multi-channel a/d converter, pulse width modulation function, power down and wake-up functions, in addition to a flexible and configurable lcd interface enhance the versatility of these devices to control a wide range of applications re - quiring analog signal processing and lcd interfacing, such as electronic metering, environmental monitoring, handheld measurement tools, motor driving, etc. for both the industrial and home appliance application areas. technical document tools information faqs application note ha0003e communicating between the ht48 & ht46 series mcus and the ht93lc46 eeprom ha0004e ht48 & ht46 mcu uart software implementation method ha0005e controlling the i2c bus with the ht48 & ht46 mcu series ha0047e an pwm application example using the ht46 series of mcus ha0075e mcu reset and oscillator circuits application note
block diagram ht46ru66/ht46cu66 rev. 1.30 2 may 25, 2011 ! " ! " # # $ # % ! & ' # ! # ( ( ! " ! " ) * * # + % $ , % * - ( . / 0 ( . 1 * , ) ! " 2 ( 2 ' 3 / ' 3 4 0 / ( ' 3 / # # * # * * , 5 # % / % / % 6 0 7 5 8 6 / ! " ' 3 4 ) ( / ) ( . / ) / ( 1 / 0 / ( 6 / 7 9 & 4 # / * - , , , ( / # ( . , 6 / # 6 # ( / , : # / , : # # / 2 # . # 6 * ! # ( / . 1 0 / " 6 / " pin assignment ht46ru66/ht46cu66 rev. 1.30 3 may 26, 2011 pin description pin name i/o configuration option description pa0/bz pa1/bz pa2 pa3/pfd pa4~pa7 i/o pull-high wake-up buzzer pfd bidirectional 8-bit input/output port. each individual pin on this port can be configured as a wake-up input by a configuration option. software in - structions determine if the pin is a cmos output or schmitt trigger input. configuration options determine which pins on the port have pull-high resistors. pins pa0, pa1 and pa3 are pin-shared with bz, bz and pfd respectively, the function of which is chosen via configuration options. pb0/an0~ pb7/an7 i/o pull-high bidirectional 8-bit input/output port. software instructions determine if the pin is a cmos output or schmitt trigger input. configuration options determine which pins on the port have pull-high resistors. pb is pin-shared with the a/d input pins. the a/d inputs are selected via soft - ware instructions. once selected as an a/d input, the i/o function and pull-high resistor functions are disabled automatically. pc0/tmr2 pc1~pc5 pc6/tx pc7/rx i/o pull-high bidirectional 8-bit input/output port. software instructions determine if the pin is a cmos output or schmitt trigger input. a configuration option determines if the port has pull-high resistors. pin pc0 is pin-shared with the timer input pin tmr2. pins pc6 and pc7 are pin-shared with the uart pins tx and rx. pd0/pwm0 pd1/pwm1 pd2/pwm2 pd3/pwm3 pd4/int0 pd5/int1 pd6/tmr0 pd7/tmr1 i/o pull-high pwm interrupt bidirectional 8-bit input/output port. software instructions determine if the pin is a cmos output or schmitt trigger input. configuration options determine which pins on the port have pull-high resistors. pd0~pd3 are pin-shared with pwm0~pwm3, the function of each pin is selected via a configuration option. pins pd4 and pd5 are pin-shared with external in - terrupt input pins int0 and int1 respectively. configuration options de- termine the interrupt enable/disable and the interrupt low/high trigger type. pins pd6 and pd7 are pin-shared with the external timer input pins tmr0 and tmr1 respectively. osc1 osc2 i o crystal or rc osc1 and osc2 are connected to an external rc network or external crystal, determined by configuration option, for the internal system clock. for external rc system clock operation, osc2 is an output pin where the system frequency can be monitored, at a frequency of 1/4 system clock. if an rtc oscillator on pins osc3 and osc4 is used as a system clock, then the osc1 and osc2 pins should be left floating. osc3 osc4 i o rtc or system clock osc3 and osc4 are connected to a 32768hz crystal to form a real time clock for timing purposes or to form a system clock. vlcd lcd power supply vmax ic maximum voltage, connect to v dd ,v lcd or v1 v1, v2, c1, c2 i lcd voltage pump seg0~seg7 o seg0~seg7 or cmos output lcd driver outputs for lcd panel segments. a configuration option can select all pins to be used as segment drivers or all pins to be used as cmos outputs. seg8~seg15 o seg8~seg15 or cmos output lcd driver outputs for lcd panel segments. a configuration option can select all pins to be used as segment drivers or all pins to be used as cmos outputs. seg16~seg23 o seg16~seg23 cmos output lcd driver outputs for lcd panel segments. configuration options can select each pin to be used as either a segment driver or each pin to be used as a cmos output. seg24~seg45 o lcd driver outputs for lcd panel segments com0~com2 com3/seg46 o 1/3 or 1/4 duty com3 or seg46 an lcd duty-cycle configuration option determines if seg46 is config - ured as a segment driver or as a common output driver for the lcd panel. com0~com2 are the lcd common outputs. ht46ru66/ht46cu66 rev. 1.30 4 may 25, 2011 pin name i/o configuration option description vref i reference voltage input pin. res i schmitt trigger reset input. active low. vdd positive power supply vss negative power supply, ground avdd i positive analog power supply avss i negative analog power supply, ground note: each pin on port a can be programmed through a configuration option to have a wake-up function. individual pins can be selected to have a pull-high resistor. pins v2, c1, c2 and segment pin seg34 are not available on the 52-pin qfp package. pins pb4/an4~pb7/an7 only exist on the 100-pin qfp package. pins pc0~pc5 only exist on the 100-pin qfp package. pin pd3/pwm3 only exists on the 100-pin qfp package. pins pd7/tmr1 and pc0/tmr2 only exist on the 100-pin qfp package. the 56-pin ssop and 52-pin qfp packages have only one external timer input tmr0. segment pins seg0~seg15 and seg35~seg45 only exist on the 100-pin qfp package. for the 52-pin qfp and 56-pin ssop, the vref, avdd are bonded together with vdd pin. for the 52-pin qfp and 56-pin ssop, the avss is bonded together with vss pin. absolute maximum ratings supply voltage ...........................v ss 0.3v to v ss +6.0v storage temperature ............................ 50 cto125 c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature........................... 40 cto85 c i ol total ..............................................................150ma i oh total............................................................ 100ma total power dissipation .....................................500mw note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage f sys =4mhz 2.2 5.5 v f sys =8mhz 3.3 5.5 v av dd analog operating voltage (see note 5) v ref =av dd 3.0 5.5 v i dd1 operating current (crystal osc, rc osc) 3v no load, f sys =4mhz, adc off, uart off 12ma 5v 35ma i dd2 operating current (crystal osc, rc osc) 3v no load, f sys =4mhz, adc off, uart on 1.5 3 ma 5v 36ma i dd3 operating current (crystal osc, rc osc) 5v no load, f sys =8mhz, adc off, uart off 48ma i dd4 operating current (crystal osc, rc osc) 5v no load, f sys =8mhz, adc off, uart on 510ma i dd5 operating current (f sys =32768hz) 3v no load, adc off, uart off 0.3 0.6 ma 5v 0.6 1 ma ht46ru66/ht46cu66 rev. 1.30 5 may 25, 2011 symbol parameter test conditions min. typ. max. unit v dd conditions i stb1 standby current (*f s =t1) 3v no load, system halt, lcd off at halt, uart off 1 a 5v 2 a i stb2 standby current (*f s =rtc osc) 3v no load, system halt, lcd on at halt, c type, uart off 2.5 5 a 5v 10 20 a i stb3 standby current (*f s =wdt osc) 3v no load, system halt, lcd on at halt, c type, uart off 25 a 5v 610 a i stb4 standby current (*f s =rtc osc) 3v no load, system halt, lcd on at halt, r type, 1 / 2 bias, v lcd =v dd , uart off (low bias current option) 17 30 a 5v 34 60 a i stb5 standby current (*f s =rtc osc) 3v no load, system halt, lcd on at halt, r type, 1 / 3 bias, v lcd =v dd , uart off (low bias current option) 13 25 a 5v 28 50 a i stb6 standby current (*f s =wdt osc) 3v no load, system halt, lcd on at halt, r type, 1 / 2 bias, v lcd =v dd , `uart off (low bias current option) 14 25 a 5v 26 50 a i stb7 standby current (*f s =wdt osc) 3v no load, system halt, lcd on at halt, r type, 1 / 3 bias, v lcd =v dd , uart off (low bias current option) 10 20 a 5v 19 40 a v il1 input low voltage for i/o ports, tmr0, tmr1, int0 and int1 0 0.3v dd v v ih1 input high voltage for i/o ports, tmr0, tmr1, int0 and int1 0.7v dd v dd v v il2 input low voltage (res ) 0 0.4v dd v v ih2 input high voltage (res ) 0.9v dd v dd v v lvr low voltage reset voltage 2.7 3.0 3.3 v v lvd low voltage detector voltage 3.0 3.3 3.6 v v ad a/d input voltage 52qfp, 56ssop 0 a vdd v 100qfp 0 v ref v v ref adc input reference voltage range av dd =3v 1.3 a vdd v av dd =5v 1.5 a vdd v i ol1 i/o port segment logic output sink current 3v v ol =0.1v dd 612 ma 5v 10 25 ma i oh1 i/o port segment logic output source current 3v v oh =0.9v dd 2 4 ma 5v 5 8 ma i ol2 lcd common and segment current 3v v ol =0.1v dd 210 420 a 5v 350 700 a i oh2 lcd common and segment current 3v v oh =0.9v dd 80 160 a 5v 180 360 a ht46ru66/ht46cu66 rev. 1.30 6 may 25, 2011 symbol parameter test conditions min. typ. max. unit v dd conditions r ph pull-high resistance of i/o ports and int0 , int1 3v 20 60 100 k 5v 10 30 50 k i adc additional power consumption if a/d converter is used 3v t ad =1s 0.5 1 ma 5v 1.5 3 ma dnl adc differential non-linear 5v av dd =5v, v ref =av dd , t ad =1s 2 lsb inl adc integral non-linear 5v av dd =5v, v ref =av dd , t ad =1s 2.5 4 lsb resolu resolution 12 bits note: 1. *f s refer to the wdt clock option 2. i stb1 =wdt disable, i stb2 ~i stb7 =wdt enable 3. voltage level of av dd and v dd must be the same. a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys1 system clock (crystal osc, rc osc) 2.2v~5.5v 400 4000 khz 3.3v~5.5v 400 8000 khz f sys2 system clock (32768hz crystal osc) 2.2v~5.5v 32768 hz f rtcosc rtc frequency 32768 hz f timer timer i/p frequency (tmr0/tmr1) 2.2v~5.5v 0 4000 khz 3.3v~5.5v 0 8000 khz t wdtosc watchdog oscillator period 3v 45 90 180 s 5v 32 65 130 s t res external reset low pulse width 1 s t sst system start-up timer period power-up or wake-up from halt 1024 t sys t int interrupt pulse width 1 s t ad a/d clock period 1 s t adc a/d conversion time 80 t ad t adcs a/d sampling time 32 t ad note: t sys = 1/f sys1 or 1/f sys2 ht46ru66/ht46cu66 rev. 1.30 7 may 25, 2011 ht46ru66/ht46cu66 rev. 1.30 8 may 25, 2011 functional description execution flow the system clock is derived from either a crystal or an rc oscillator or a 32768hz crystal oscillator. it is inter - nally divided into four non-overlapping clocks. one in - struction cycle consists of four system clock cycles. instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while de - coding and execution takes the next instruction cycle. the pipelining scheme allows each instruction to be ef - fectively executed in a cycle. if an instruction changes the value of the program counter, two cycles are re - quired to complete the instruction. program counter pc the program counter is 14 bits wide and controls the se - quence in which the instructions stored in the program rom are executed. the contents of the pc can specify a maximum of 16384 16 addresses. after accessing a program memory word to fetch an in - struction code, the value of the pc is incremented by 1. the pc then points to the memory word containing the next instruction code. when executing instructions requiring jumps to non-consecutive addresses such as a jump instruc - tion,a subroutine call, interrupt or reset, etc., the 2 & * * < = > * * < 9 = 2 & * * < ? = > * * < = 2 & * * < ? = > * * < ? = ? ? $ * 4 @ * < * 4 $ = execution flow mode program counter *13 *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 initial reset 00000000000000 external interrupt 0 00000000000100 external interrupt 1 00000000001000 timer/event counter 0 overflow 00000000001100 timer/event counter 1 overflow 00000000010000 uart bus interrupt 00000000010100 multi-function interrupt 00000000011000 skip program counter + 2 (within the current bank) loading pcl *13 *12 *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch bp.5 #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: *13~*0: program counter bits s13~s0: stack register bits #12~#0: instruction code bits @7~@0: pcl bits 7 6 ( , a 1 ! " # ht46ru66/ht46cu66 rev. 1.30 9 may 25, 2011 microcontroller manages program control by loading the required address into the program counter. for condi - tional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is dis - carded and a dummy cycle takes its place while the cor - rect instruction is obtained. the lower byte of the program counter, known as the program counter low register or pcl, is available for program control and is a readable and writable register. by transferring data directly into this register, a short pro - gram jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 loca - tions. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. as the program memory is stored in two banks, the bank selection is under the control of bit 5 of the bank pointer. it is this bank pointer bit that controls the highest address bit of the program counter as shown in the diagram. program memory the program memory is used to store the program in - structions, which are to be executed. it also contains data, table, and interrupt entries, and is organized into a format of 16384 16 bits, which are addressed by the pc and table pointer. the program memory is divided into two banks, bank0 and bank1. each bank has a capacity of 8192 16 bits and is selected using bit bp.5 in the the bank pointer register. with bp = 000xxxxxb, bank0 is se- lected and with bp = 001xxxxxb, bank1 is selected. the jmp and call instructions provide only 13 bits of ad- dress to allow branching within any 8k program memory bank. when executing a jmp or call instruction, the user must ensure that the bank pointer bit, bp.5, is pro - grammed so that the desired program memory bank is addressed. if a return from a call instruction or inter - rupt is executed, the entire 14 bit pc is popped off the stack. therefore, manipulation of the bp.5 is not re - quired when the ret or reti instructions are executed. certain locations in the program memory are reserved for special usage: location 000h location 000h is reserved for program initialisation. after a device reset, the program will jump to this loca - tion and begin execution. location 004h location 004h is reserved for the external interrupt service program. if the int0 input pin is activated, the interrupt is enabled, and the stack is not full, the pro - gram begins execution at location 004h. location 008h location 008h is also reserved for the external inter - rupt service program. if the int1 input pin is activated, the interrupt is enabled, and the stack is not full, the program will jump to this location and begin execution. location 00ch location 00ch is reserved for the timer/event coun- ter 0 interrupt service program. if a timer interrupt re- sults from a timer/event counter 0 overflow, and if the interrupt is enabled and the stack is not full, the pro- gram will jump to this location and begin execution. location 010h location 010h is reserved for the timer/event coun - ter 1 interrupt service program. if a timer interrupt re - sults from a timer/event counter 1 overflow, and if the interrupt is enabled and the stack is not full, the pro - gram will jump to this location and begin execution. location 014h location 014h is reserved for the uart bus interrupt service program. if the uart bus interrupt resulting from a transmission flag or reception is completed, and if the interrupt is enabled and the stack is not full, the program will jump to this location and begin execution. instruction(s) table location **13~*8 *7 *6 *5 *4 *3 *2 *1 *0 tabrdc [m] tbhp @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 111111 @7 @6 @5 @4 @3 @2 @1 @0 table location note: *13~*0: table location bits tbhp: table pointer higher-order bits @7~@0: table pointer lower-order bits (tblp) - * 4 8 * > 4 * * ( * b / - * * ( * * b $ < 7 ; * , @ = % @ 9 * b 4 * < 1 0 * c = d * * * ' * ( * * 2 > 4 * * * b ! # * , * 4 9 2 * % @ 9 * b 4 * < 1 0 * c = 0 * b / - * * * * b ( ( ( 5 ( ( 5 ( ( 7 5 ( 5 2 2 2 5 ( 7 5 ( ( 5 ( ( 5 2 2 5 ( ( 5 2 ( ( 5 program memory ht46ru66/ht46cu66 rev. 1.30 10 may 25, 2011 location 018h this area is reserved for the multi-function interrupt service program. if a timer interrupt results from a timer/event counter 2 overflow, or the real time clock time out, or time base time out, and if the interrupt is enabled and the stack is not full, the program will jump to this location and begin execution. table location any location in the program memory can be used as a look-up table. the instructions tabrdc [m] (page specified by the tbhp) for the current page, 1 page=256 words) and tabrdl [m] (the last page), transfer the contents of the lower-order byte to the specified data memory, and the contents of the higher-order byte to the tblh register. this is the ta - ble higher-order byte register (08h). only the destina - tion of the lower-order byte in the table is well-defined, the other bits of the table word are all transferred to the lower portion of the tblh. the tblh is read only, the higher-order byte table pointer tbhp (1fh) and the table pointer, tblp, is a read/write register (07h), indicating the table location. before accessing the ta - ble, the location should be placed in the tbhp and tblp registers. all the table related instructions re - quire 2 cycles to complete the operation. these areas may function as a normal program memory depend - ing upon the user s requirements. stack register stack the stack register is a special part of the memory used to save the contents of the program counter. the stack is organized into 16 levels and is neither part of the data nor part of the program, and is neither readable nor writeable. its activated level is indexed by a stack pointer, known as sp, which is neither readable nor writeable. at the start of a subroutine call or an interrupt acknowledgment, the contents of the program counter is pushed onto the stack. at the end of the subroutine or interrupt routine, signaled by a return instruction, ret or reti, the contents of the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and a non-masked interrupt takes place, the interrupt request flag is recorded but the ac - knowledge signal is still inhibited. once the sp is decre - mented, using an ret or reti instruction, the interrupt is serviced. this feature prevents stack overflow, allow - ing the programmer to use the structure easily. like - wise, if the stack is full, and a call is subsequently executed, a stack overflow occurs and the first entry is lost as only the most recent 16 return addresses are stored. data memory ram the data memory, ram, has a structure of 620 8 bits, and is divided into two functional groups, namely; spe - cial function registers, 44 8 bits, and general purpose data memory (bank 0: 192 8 bits, bank 2: 192 8 bits 4 * * $ d * ! * * e ( ( e 4 * * $ ; * , $ * < * , @ d * , @ ( f * , @ f * , @ = 2 2 5 ( 5 * # * * ( ( * # * * , # % , % , % 5 # ! ( ( 5 ( % ( 5 % # # , , ) ( ) ) ) , 5 # % # 5 # # 2 ! ! ! " / " , ( ( 5 ( 5 ( 5 ( 5 ( 5 ( 1 5 ( 0 5 ( 6 5 ( 7 5 ( ; 5 ( # 5 ( , 5 ( 5 ( 5 ( 5 ( 2 5 ( 5 5 5 5 5 1 5 0 5 6 5 7 5 ; 5 # 5 , 5 5 5 5 2 5 ( 5 5 5 5 5 1 5 0 5 6 5 7 5 ; 5 # 5 , 5 5 5 5 2 5 ( 5 5 5 5 5 1 5 2 5 ram mapping ht46ru66/ht46cu66 rev. 1.30 11 may 25, 2011 and bank 3: 192 8 bits). most of these registers are readable and writeable, although some are read only. the special function registers are overlapped in any bank. of the two types of functional groups, the special function registers consist of an indirect addressing reg - ister 0 (00h), a memory pointer register 0 (mp0;01h), an indirect addressing register 1 (02h), a memory pointer register 1 (mp1;03h), a bank pointer (bp;04h), an accumulator (acc;05h), a program counter lower-order byte register (pcl;06h), a table pointer lower-order byte (tblp;07h), a table pointer higher-or - der byte (tbhp;1fh), a table higher-order byte register (tblh;08h), a real time clock control register (rtcc;09h), a status register (status;0ah), an inter - rupt control register 0 (intc0;0bh), a timer/event counter 0 (tmr0h;0ch; tmr0l;0dh), a timer/event counter 0 control register (tmr0c;0eh), a timer/event counter 1 (tmr1h:0fh;tmr1l;10h), a timer/event counter 1 control register (tmr1c;11h), a timer/event counter 2 (tmr2;2dh), a timer/event counter 2 con - trol register (tmr2c;2eh), interrupt control register 1 (intc1;1eh), multi-function interrupt control register 1 (mfic;2fh), pwm data register (pwm0;1ah, pwm1;1bh, pwm2;1ch, pwm3;1dh), the a/d result lower-order byte register (adrl;24h), the a/d result higher-order byte register (adrh;25h), the a/d control register (adcr;26h), the a/d clock setting register (acsr;27h), i/o registers (pa;12h, pb;14h, pc;16h, pd;18h) and i/o control registers (pac;13h, pbc;15h, pcc;17h, pdc;19h), the uart bus status register control register (usr;30h), the uart bus control regis- ter 1 (ucr1;31h), the uart bus control register 2 (ucr2;32h), the uart bus transmit and receive regis- ter (txr/rxr;33h), the uart bus baud rate genera- tor register (brg;34h). the data memory space before address 40h is re - served for future expansion usage and reading these lo - cations will retrieve a value of 00h . the space before 40h overlaps in each bank. the general purpose data memory, addressed from 40h to ffh (bank0; bp=0, bank2; bp=2 or bank3; bp=3), is used for data and con - trol information under instruction commands. all of the data memory areas can directly handle arithmetic, logic, increment, decrement and rotate operations . except for some dedicated bits, each bit in the data memory can be set and reset by set [m].i and clr [m].i . they are also indirectly accessible through the memory pointer registers, mp0;01h and mp1;03h. indirect addressing register location 00h and 02h are indirect addressing registers that are not physically implemented. any read/write op - eration of [00h] and [02h] accesses the data memory pointed to by mp0 and mp1 respectively. reading loca - tion 00h or 02h indirectly returns the result 00h. writing to it indirectly results to no operation. the function of data movement between two indirect ad - dressing registers is not supported. the memory pointer registers, mp0 and mp1, are both 8-bit registers used to access the data memory in combination with their corre - sponding indirect addressing registers. mp0 can only be used to access data from bank 0, while mp1 can be used to access data from all banks. accumulator acc the accumulator, acc, is related to the alu operations. it is also mapped to location 05h of the data memory, and is capable of operating with immediate data. the data movement between two data memory locations must pass through the acc. arithmetic and logic unit alu this circuit performs 8-bit arithmetic and logic opera - tions and provides the following functions: arithmetic operations (add, adc, sub, sbc, daa) logic operations (and, or, xor, cpl) rotation (rl, rr, rlc, rrc) increment and decrement (inc, dec) branch decision (sz, snz, siz, sdz, etc.) the alu not only saves the results of a data operation but also changes the status register. status register status the status register (0ah) is 8 bits wide and contains, a carry flag (c), an auxiliary carry flag (ac), a zero flag (z), an overflow flag (ov), a power down flag (pdf), and a watchdog time-out flag (to). it also records the status information and controls the operational sequence. except for the to and pdf flags, bits in the status reg- ister can be altered by instructions similar to the other registers. data written into the status register does not alter the to or pdf flags. operations related to the sta - tus register, however, may yield different results from those intended. the to and pdf flags can only be changed by a watchdog timer overflow, device power-up, or clearing the watchdog timer and execut - ing the halt instruction. the z, ov, ac, and c flags reflect the status of the latest operations. on entering the interrupt sequence or executing a sub - routine call, the status register will not be automatically pushed onto the stack. if the contents of the status is im - portant, and if the subroutine is likely to corrupt the sta - tus register, the programmer should take precautions to save it properly. ht46ru66/ht46cu66 rev. 1.30 12 may 25, 2011 bit no. label function 0c c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation, otherwise c is cleared. c is also affected by a ro - tate through carry instruction. 1ac ac is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction, otherwise ac is cleared. 2 z z is set if the result of an arithmetic or logic operation is zero, otherwise z is cleared. 3ov ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa, otherwise ov is cleared. 4 pdf pdf is cleared by either a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. 5to to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. 6, 7 unused bit, read as 0 status (0ah) register interrupts intc0, intc1, mfic the device provides two external interrupts, two internal timer/event counter (0/1) interrupts, a uart bus inter - rupt, and a multi-function interrupt. the multi-function in - terrupt includes the internal timer/event counter 2 interrupt, the internal real time clock interrupt, and the internal time base interrupt . the interrupt control regis - ter 0, intc0;0bh, interrupt control register 1, intc1;1eh, and the multi-function interrupt control register, mfic;2fh, contain the interrupt control bits that are used to set the enable/disable status and inter- rupt request flags. once an interrupt subroutine is serviced, other inter- rupts are all blocked automatically as the emi bit is cleared. this scheme may prevent any further interrupt nesting. other interrupt requests may take place during this interval, but only the interrupt request flag will be re - corded. if a certain interrupt requires servicing within the service routine, the emi bit and the corresponding bits in the intc0, intc1 and mfic registers may be set in or - der to allow interrupt nesting. once the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the sp is decremented. if immediate service is desired, the stack should be pre - vented from becoming full. all these interrupts can support a wake-up function. as an interrupt is serviced, a control transfer occurs by pushing the contents of the program counter onto the stack followed by a branch to a subroutine at the speci - fied location in the program memory. only the contents of the program counter is pushed onto the stack. if the contents of the register or the status register is altered by the interrupt service program which corrupts the de - sired control sequence, the contents should be saved in advance. external interrupts are triggered by an edge transition on pins int0 or int1 . a configuration option exists to select one of three transition types, either high to low, low to high or both. the related interrupt request flag, eif0; bit 4 of the intc0 register and eif1; bit 5 of the intc0 register, will be set when an external interrupt oc - curs. after the interrupt is enabled, the stack is not full, and the external interrupt is active, a subroutine call to location 04h or 08h occurs. the interrupt request flag, eif0 or eif1 and the emi bits are all cleared to disable other maskable interrupts. the internal timer/event counter 0 interrupt is initial- ised by setting the timer/event counter 0 interrupt re- quest flag, t0f; bit 6 of the intc0 register, which is normally caused by a timer overflow. after the interrupt is enabled, and the stack is not full, and the t0f bit is set, a subroutine call to location 0ch occurs. the re- lated interrupt request flag, t0f, is reset, and the emi bit is cleared to disable other maskable interrupts. the timer/event counter 1 and timer/event counter 2 operates in the same manner, the timer/event counter 1 related interrupt request flag is t1f, bit 4 of the intc1 register, and its subroutine call location is 010h. the timer/event counter 2 related interrupt request flags are mff, bit 6 of the intc1 register, and t2f, bit 4 of the mfic register, and its subroutine call location is 018h. the related interrupt request flags, t1f and mff, will be reset and the emi bit cleared to disable further inter - rupts. t2f, bit 4 of the mfic register, will not be cleared automatically, and should be cleared by the user. the uart bus interrupt is initialized by setting the uart bus interrupt request flag, urf; bit 5 of the intc1 register, caused by transmit data register empty (txif), received data available(rxif), transmission idle (tidle), over run error (oerr) or address detected. when the interrupt is enabled, the stack is not full and the txif, rxif, tidle, oerr bit is set or an address is detected, a subroutine call to location 014h will occur. the related interrupt request flag, urf, will be reset and the emi bit cleared to disable further interrupts. ht46ru66/ht46cu66 rev. 1.30 13 may 25, 2011 the multi-function interrupt, mfi, is initialised by setting the interrupt request flag, mff; bit 6 of the intc1 regis - ter, that is caused by a timer 2 overflow, t2f; bit 4 of the mfic register, caused by a regular real time clock time-out, rtf; bit 6 of the mfic register or caused by a time base time-out, tbf; bit5 of the mfic register. after the interrupt is enabled, emfi=1, the stack is not full, and the mff bit is set, a subroutine call to location 018h will occur. the related interrupt request flag, mff, is re - set and the emi bit is cleared to disable further maskable interrupts. t2f, tbf and rtf indicate that a related interrupt has occurred. as these flags will not be cleared automatically after reading, they should be cleared by the user. during the execution of an interrupt subroutine, other maskable interrupt acknowledgments are all held until the reti instruction is executed or the emi bit and the related interrupt control bit are set both to 1, if the stack is not full. to return from the interrupt subroutine, a ret or reti instruction may be executed. reti sets the emi bit and enables an interrupt service, but ret does not. interrupts occurring in the interval between the rising edges of two consecutive t2 pulses are serviced on the latter of the two t2 pulses if the corresponding interrupts are enabled. in the case of simultaneous requests, the priorities in the following table apply. these can be masked by resetting the emi bit. bit no. label function 0 emi controls the master (global) interrupt (1=enable; 0= disable) 1 eei0 controls the external interrupt 0 (1=enable; 0=disable) 2 eei1 controls the external interrupt 1 (1=enable; 0=disable) 3 et0i controls the timer/event counter 0 interrupt (1=enable; 0=disable) 4 eif0 external interrupt 0 request flag (1=active; 0=inactive) 5 eif1 external interrupt 1 request flag (1=active; 0=inactive) 6 t0f internal timer/event counter 0 request flag (1=active; 0=inactive) 7 for test mode used only. must be written as 0 ; otherwise may result in unpredictable operation. intc0 (0bh) register bit no. label function 0 et1i controls the timer/event counter 1 interrupt (1=enable; 0=disable) 1 euri control the uart bus interrupt (1=enable; 0=disable) 2 emfi control the multi-function interrupt (1=enable; 0=disable) 3, 7 unused bit, read as 0 4 t1f internal timer/event counter 1 request flag (1=active; 0=inactive) 5 urf uart bus request flag (1=active; 0=inactive) 6 mff multi-function interrupt request flag (1=active; 0=inactive) intc1 (1eh) register bit no. label function 0 et2i control the timer/event counter 2 interrupt (1=enable; 0=disable) 1 etbi control the time base interrupt (1=enable; 0=disable) 2 erti control the real time clock interrupt (1=enable; 0=disable) 3, 7 unused bit, read as 0 4 t2f timer/event counter 2 interrupt request flag (1=active; 0=inactive) 5 tbf time base interrupt request flag (1=active; 0=inactive) 6 rtf real time clock interrupt request flag (1=active; 0=inactive) mfic (2fh) register ht46ru66/ht46cu66 rev. 1.30 14 may 25, 2011 interrupt source priority vector external interrupt 0 1 04h external interrupt 1 2 08h timer/event counter 0 overflow 3 0ch timer/event counter 1 overflow 4 10h uart bus interrupt 5 14h multi-function interrupt (timer/event counter 2 / real time clock / time base overflow) 6 18h the timer/event counter 0 interrupt request flag, t0f, the external interrupt 1 request flag, eif1, the external interrupt 0 request flag, eif0, the enable timer/event counter0 interrupt bit, et0i, the enable external inter - rupt 1 bit, eei1, the enable external interrupt 0 bit, eei0, and the enable master interrupt bit, emi, make up the in - terrupt control register 0, intc0, which is located at 0bh in the program memory. the multi-function interrupt request flag, mff, the uart interrupt request flag, urf, the timer/event counter 1 interrupt request flag, t1f, the enable multi-function in - terrupt bit, emfi, and the enable uart interrupt bit, euri, and the enable timer/event counter 1 interrupt bit, et1i, constitute the interrupt control register 1, intc1, which is located at 1eh in the program memory. the time base interrupt request flag, tbf, the real time interrupt request flag, rtf, the timer/event counter 2 interrupt request flag, t2f, the enable time base inter- rupt bit, etbi, the enable real time interrupt bit, erti, and the enable timer/event counter 2 interrupt bit, et2i, constitute the multi-function interrupt control register, mfic, which is located at 2fh in the program memory. the emi, eei0, eei1, et0i, et1i, euri and emfi bits are used to control the enabling/disabling of interrupts. these bits prevent the requested interrupt from being serviced. once the interrupt request flags, eif0, eif1, t0f, t1f, urf, mff, are set, they will remain in the intc0 and intc1 registers until the interrupts are ser - viced or cleared by a software instruction. the timer/event counter 2 overflow interrupt flag, t2f; bit 4 of the mfic register, the real time clock interrupt flag, rtf; bit 6 of the mfic register, the time base inter - rupt flag, tbf; bit 5 of the mfic register, indicate that a related interrupt has occurred. as these flags will not be cleared automatically, they should be cleared by the user. the enable control timer 2 interrupt, et2i, the en - able time base interrupt, etbi, the enable real time clock interrupt, erti, constitute the interrupt control register 2, mfic, which is located at 2fh in the pro - gram memory. it is recommended that a program does not use the call instruction within the interrupt subroutine. inter - rupts often occur in an unpredictable manner or need to be serviced immediately in some applications. if only one stack is left and the interrupt enabling is not well controlled, the original control sequence may be dam - aged if a call is executed. oscillator configuration the device provides three oscillator circuits for system clocks. these are an rc oscillator, a crystal oscillator and a 32768hz crystal oscillator, the choice of which is determined by a configuration option. the power down mode will stop the system oscillator, if it is an rc or crys - tal oscillator type and will ignore external signals in order to conserve power. if the 32768hz crystal oscillator is selected as the system oscillator, it will continue to run in the power down mode, but the instruction execution will be stopped. since the 32768hz oscillator is also de- signed for timing purposes, the internal timing (rtc, time base, wdt) operation still runs even if the system enters the power down mode. of the three oscillators, if the rc oscillator is used, an external resistor between osc1 and vss is required, whose range should be within 24k to 1m . the sys- tem clock frequency divided by 4, can be monitored on pin osc2 if a pull-high resistor is added. this can be used to synchronise external logic. the rc oscillator provides the most cost effective solution. however, the frequency of the oscillation may vary with vdd, temper - ature, and the chip itself due to process variations. it is therefore, not suitable for timing sensitive operations where accurate an oscillator frequency is desired. $ 4 * 4 4 6 0 7 5 8 * $ 4 / * 4 4 * 4 4 ' 3 / 6 ( 2 system oscillator note: 32768hz crystal enable condition: for wdt clock source or for system clock source. the external resistor and capacitor components connected to the 32768hz crystal are not necessary to pro - vide oscillation. for applications where precise rtc frequencies are essential, these components may be re - quired to provide frequency compensation due to different crystal manufacturing tolerances. ht46ru66/ht46cu66 rev. 1.30 15 may 25, 2011 if the crystal oscillator is to be used, a crystal across osc1 and osc2 is needed to provide the feedback and phase shift required for oscillation, no other external components are required. a resonator may be con - nected between osc1 and osc2 to replace the crystal and to get a frequency reference, but two external ca - pacitors must be be connected between osc1, osc2 and ground. the other oscillator circuit is for the real time clock or rtc, which has a fixed frequency of 32.768khz. a 32.768khz crystal oscillator should be connected be - tween osc3 and osc4 for its implementation. the rtc oscillator circuit has a quick start up function which can be activated by setting the qosc bit, which is bit 4 of the rtcc register. it is recommended to turn this bit on at power on, and then turn it off after 2 sec - onds to conserve power. the wdt oscillator is a free running on-chip rc oscilla - tor, which requires no external components. when the system enters the power down mode, the system clock will stop, but the wdt oscillator will continue to operate, with a period of approximately 65 s at 5v. the wdt os - cillator can be disabled by a configuration option to con - serve power. watchdog timer wdt the wdt clock source can come from its own dedicated internal wdt oscillator, from the instruction clock (sys- tem clock/4), or from the real time clock oscillator (rtc oscillator). the timer is designed to prevent software malfunctions or sequences from jumping to unknown lo- cations with unpredictable results. the wdt can be dis- abled by a configuration option. if the wdt is disabled, all executions related to the wdt result in no operation. the wdt clock source is divided by 2 12 ~2 15 , the actual value chosen by a configuration option, to get the wdt time-out period. for the wdt internal oscillator, the min - imum wdt time-out period is about 300ms~600ms. this time-out period may vary with temperature, vdd and process variations. by using configuration options to set the wdt prescaler, longer time-out periods can be realised. if the wdt time-out is selected as 2 15 , the maximum time-out period is divided by 2 15 ~2 16 . this will give a time of about 2.1s~4.3s for the internal wdt os - cillator. if the wdt oscillator is disabled, the wdt clock may still come from the instruction clock. the wdt will operate in the same manner except that in the power down mode, the wdt will stop counting and lose its pro - tecting purpose. in this situation the system can only be restarted by external logic. if the device operates in a noisy environment, using the on-chip wdt internal os - cillator is strongly recommended, since the power down mode will stop the system clock. a wdt overflow under normal operation initialises a device reset and sets the status bit to . in the power down mode, the overflow initialises a warm reset , and only the program counter and stack pointer are reset to zero. to clear the wdt contents, three methods can be adopted. these are an external reset which is a low level to res , a software instruction, and a halt in - struction. there are two types of software instructions; the single clr wdt instruction and the instruction pair clr wdt1 and clr wdt2 . of these two types of instruction, only one type of instruction can be active at a time depending on the options clr wdt times selection option. if the clr wdt is selected, i.e., clr wdt times equal one, any execution of the clr wdt instruction clears the wdt. in the case that clr wdt1 and clr wdt2 are chosen, i.e., clr wdt times equal two, these two instructions have to be executed to clear the wdt, otherwise, the wdt may re- set the device due to a time-out. multi-function timer the device provides a multi-function timer for the wdt, time base and the rtc but with different time-out peri- ods. the multi-function timer consists of an 8-stage di- vider and a 7-bit prescaler, with the clock source coming from the wdt osc or rtc osc or the instruction clock (i.e., system clock divided by 4). the multi-function timer also provides a selectable frequency signal (ranging from f s /2 2 to f s /2 8 ) for the lcd driver circuits, and a selectable frequency signal, ranging from f s /2 2 to f s /2 9 , for the buzzer output, setup by configuration options. it is recommended to select a frequency as near to 4khz as possible for the lcd driver circuits for clarity. $ * 4 @ / ) * 4 ' ' / 7 9 * ' / 1 . ' / 0 ' / . ' / 1 ' / . ' / ' / . ' / - ) 4 @ * + + ) @ 5 8 6 0 7 5 8 watchdog timer ht46ru66/ht46cu66 rev. 1.30 16 may 25, 2011 time base the time base offers a periodic time-out period to gener - ate a regular internal interrupt. its time-out period ranges from 2 12 /f s to 2 15 /f s selected by options. if a time base time-out occurs, the related interrupt request flags, tbf; bit 5 of the mfic register, and mff; bit 6 of the intc1 register, will be set. if the interrupt is enabled, and the stack is not full, a subroutine call to location 18h occurs. the time base time-out signal can also be ap - plied as a clock source for the timer/event counter 1 to obtain longer time-out periods. real time clock rtc the real time clock operates in the same manner as the time base in that it is used to supply a regular internal in - terrupt. its time-out period ranges from f s /2 8 to f s /2 15 , the actual value of which is setup by software program- ming. writing data to the rt2, rt1 and rt0 bits in the rtcc register, provides various time-out periods. if an rtc time-out occurs, the related interrupt request flag, rtf; bit 6 of the mfic and mff; bit 6 of the intc1, is set. if the interrupt is enabled, and the stack is not full, a subroutine call to location 18h occurs. the real time clock time-out signal can also be applied as a clock source for timer/event counter 0 in order to get longer time-out period. rt2 rt1 rt0 rtc clock divided factor 000 2 8 * 001 2 9 * 010 2 10 * 011 2 11 * 100 2 12 101 2 13 110 2 14 111 2 15 note: * not recommended to be used power down operation halt the power down mode is initialised by the halt in - struction and results in the following. the system oscillator turns off but the wdt oscillator keeps running if the internal wdt oscillator or the real time clock is selected. the contents of the on-chip ram and of the registers remain unchanged. the wdt is cleared and starts recounting, if the wdt clock source comes from the wdt oscillator or the real time clock oscillator. all i/o ports maintain their original status. the pdf flag is set but the to flag is cleared. the lcd driver keeps running, if the wdt osc or rtc osc is selected. the system leaves the power down mode by way of an external reset, an interrupt, an external falling edge sig - nal on port a, or a wdt overflow. an external reset causes device initialisation, and a wdt overflow per - forms a warm reset . after examining the to and pdf flags, the reason behind the chip reset can be deter - mined. the pdf flag is cleared by a system power-up or by executing the clr wdt instruction, and is set by executing the halt instruction. the to flag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, and leaves the other registers in their original state. a port a wake-up and interrupt methods can be consid- ered as a continuation of normal execution. each bit in port a can be independently selected to wake up the de- vice via configuration options. awakening from an i/o port stimulus, the program resumes execution of the next instruction. on the other hand, awakening from an interrupt, two sequence may occur. if the related inter - rupt is disabled or the interrupt is enabled but the stack is full, the program resumes execution at the next in - struction. but if the interrupt is enabled, and the stack is not full, the regular interrupt response takes place. when an interrupt request flag is set before entering the halt state, the system cannot be awakened using that interrupt. if wake-up events occur, it takes 1024 t sys (system clock period) to resume normal operation. in other words, a dummy period is inserted after a wake-up. if a wake-up results from an interrupt acknowledge, the ac - tual interrupt subroutine execution is delayed by more than one cycle. however, if a wake-up results in the next instruction execution, the execution will be performed immediately after the dummy period has finished. to minimize power consumption, all the i/o pins should be carefully managed before entering the power down state. - * * * * ' 7 * * * ! " 4 ( * 7 / ' . 1 / ' real time clock * * * * * * * * ' - 4 * * % * - * < ' / . ' / 7 = , 8 8 * < ' / . ' / ; = * , * ' / . ' / 1 time base ht46ru66/ht46cu66 rev. 1.30 17 may 25, 2011 reset there are several ways in which a reset may occur. res is reset during normal operation power on reset res is reset during a power down wdt time-out is reset during normal operation wdt time-out during a power down a wdt time-out when the device is in the power down mode differs from the other reset conditions, as it per - forms a warm reset that resets only the program coun - ter and sp and leaves the other circuits in their original state. some registers remain unaffected during the other reset conditions. most registers are reset to their initial condition once the reset conditions are met. by ex - amining the pdf and to flags, the program can distin - guish between the different types of resets. to pdf reset conditions 0 0 res reset during power-up u u res reset during normal operation 0 1 res wake-up halt 1 u wdt time-out during normal operation 1 1 wdt wake-up halt note: u stands for unchanged to guarantee that the system oscillator has started and stabilized, the sst (system start-up timer) provides an extra delay of 1024 system clock pulses when the sys- tem awakens from the power down mode or during power up. the functional unit chip reset status is shown below. program counter 000h interrupt disabled prescaler, divider cleared wdt, rtc, time base cleared. after a master reset, the wdt starts counting timer/event counter off input/output ports input mode stack pointer points to the top of the stack ( ( @ ( @ ( a ( 2 ( ( @ ( a 2 ( a 2 $ ! % $ ! % ! ! ! $ $ ! % ! reset circuit note: most applications can use the basic reset cir- cuit as shown, however for applications with ex- tensive noise, it is recommended to use the hi-noise reset circuit. * 9 & * * reset timing chart ) 5 # % ) 9 > 4 4 c 9 * ( 9 b * 4 ) * reset configuration ht46ru66/ht46cu66 rev. 1.30 18 may 25, 2011 the register states are summarized below: register reset (power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu bp 0000 0000 0000 0000 0000 0000 0000 0000 00u0 00uu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu program counter 0000h 0000h 0000h 0000h 0000h tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu rtcc --00 0111 --00 0111 --00 0111 --00 0111 --uu uuuu status --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu intc0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tmr0h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr0l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr0c 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu tmr1h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr1l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr1c 0000 1--- 0000 1--- 0000 1--- 0000 1--- uuuu u--- pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pcc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pd 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pdc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pwm0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu pwm1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu pwm2 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu pwm3 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu intc1 -000 -000 -000 -000 -000 -000 -000 -000 -uuu -uuu tbhp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu adrl xxxx ---- xxxx ---- xxxx ---- xxxx ---- uuuu ---- adrh xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adcr 0100 0000 0100 0000 0100 0000 0100 0000 uuuu uuuu acsr 1--- --00 1--- --00 1--- --00 ---- --00 u--- --uu tmr2 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr2c 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu mfic -000 -000 -000 -000 -000 -000 -000 -000 -uuu -uuu usr 0000 1011 0000 1011 0000 1011 0000 1011 uuuu uuuu ht46ru66/ht46cu66 rev. 1.30 19 may 25, 2011 register reset (power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* ucr1 0000 00x0 0000 00x0 0000 00x0 0000 00x0 uuuu uuuu ucr2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu txr/rxr xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu brg xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu note: * stands for warm reset u stands for unchanged x stands for unknown timer/event counter three timer/event counters are implemented in this microcontroller. the timer/event counter 0 contains a 16-bit programmable count-up counter whose clock may come from an external or internal source. its inter - nal clock source comes from f sys . the timer/event counter 1 contains a 16-bit programmable count-up counter whose clock may come from an external or in - ternal source. its internal clock source comes from ei - ther f sys /4 or the 32768hz rtc oscillator selected via configuration option. the timer/event counter 2 con - tains an 8-bit programmable count-up counter whose clock may come from an external or internal source. its internal clock source comes from f sys . the external clock input allows the user to count external events, measure time intervals or pulse widths, or generate an accurate time base. there are eight registers related to the timer/event counter 0; tmr0h (0ch), tmr0l (0dh), tmr0c (0eh) and the timer/event counter 1; tmr1h (0fh), tmr1l (10h), tmr1c (11h) and the timer/event counter 2; tmr2 (2ch) tmr2c (2dh). writing to tmr0l (tmr1l) will only put the written data into an in - ternal lower-order byte buffer (8-bit) while writing to tmr0h (tmr1h) will transfer the specified data and the contents of the lower-order byte buffer into the tmr0h (tmr1h) and tmr0l (tmr1l) registers, respectively. the timer/event counter 1/0 preload register is changed by each write operation to tmr0h (tmr1h). reading from the tmr0h (tmr1h) will latch the con - tents of the tmr0h (tmr1h) and tmr0l (tmr1l) counters to the destination and the lower-order byte buffer, respectively. reading from tmr0l (tmr1l) will read the contents of the lower-order byte buffer. writing to tmr2 places the start value into the timer/event counter 2 preload register, and reading from tmr2 re - trieves the contents of the timer/event counter 2. the tmr0c (tmr1c,tmr2c) register is the timer/event counter 0 (1, 2) control register, which defines the oper - ating mode, enable or disable function and the active edge. the t0m0, t0m1 (tmr0c), t1m0, t1m1 (tmr1c) and t2m0, t2m1 (tmr2c) bits define the operational mode. the event count mode is used to count external events, which means that the clock source comes from the ex - ternal, tmr0, tmr1 or tmr2 pin. the timer mode func - tions as a normal timer with the clock source coming from the internally selected clock source. finally, the pulse width measurement mode can be used to count the duration of a high or low level external signal on pin tmr0, tmr1 or tmr2. the counting is based on the in - ternally selected clock source. in the event count or timer mode, the timer/event coun - ter 0 (1) starts counting at the current contents in the timer/event counter and ends at ffffh. timer/event counter 2 starts counting at the current contents in the timer/event counter and ends at ffh. once an overflow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt re- quest flag which are t0f; bit 6 of intc0, t1f; bit 4 of intc1, t2f; bit 4 of mfic and bit 6 of intc1. to enable the pulse width measurement mode, the op- erating mode select bits should both be set high. after the tmr0/tmr1/tmr2 pin has received a transient from low to high, or high to low if the t0e/t1e/t2e bit is 0 , it will start counting until the tmr0/tmr1/ tmr2 pin returns to its original level a which point the t0on/t1on/t2on bit will be auomatically reset. the measured result remains in the timer/event counter even if the activated transient occurs again. in other words, only a single shot measurement can be made. not until the t0on/t1on/t2on bit is again set by the program, can further pulse width measurements be made. in this operation mode, the timer/event counter begins counting not according to the logic level but to the transient edges. in the case of counter overflows, the counter is reloaded from the timer/event counter register and issues an interrupt request, as in the other two modes, i.e., event and timer modes. to enable the counting operation, the timer on bit, t0on; bit 4 of tmr0c, t1on; bit 4 of tmr1c, or t2on; bit 4 of tmr2c, should be set to 1. in the pulse width measurement mode, the t0on/t1on/ t2on is auto - matically cleared after a measurement cycle is com - pleted. but in the other two modes, the t0on/t1on/t2on can only be reset by instructions. ht46ru66/ht46cu66 rev. 1.30 20 may 25, 2011 the overflow of the timer/event counter 0/1/2 is one of the wake-up sources. the timer/event counter 0/1 can also be applied to a pfd or programmable frequency divider whose output is on pin pa3 via a configuration option. only one pfd (pfd0 or pfd1) can be applied to pa3 by options. no matter what the operation mode is, writing a 0 to et0i, et1i or et2i disables the related interrupt service. when the pfd function is selected, ex - ecuting the set [pa].3 instruction will enable the pfd output and executing the clr [pa].3 instruction will disable the pfd output. if the timer/event counter is not running, writing data to the timer/event counter preload register will also reload that data to the timer/event counter. but if the timer/event counter running, data written to the timer/event counter is kept only in the timer/event coun - ter preload register. the timer/event counter continues to operate until an overflow occurs at which point the new data will be loaded from the preload register into the timer/event counter. after the timer has been initialised the timer can be turned on and off by controlling the enable bit in the timer control register. note that setting the timer enable bit high to turn the timer on, should only be executed af - ter the timer mode bits have been properly setup. set - ting the timer enable bit high together with a mode bit modification, may lead to improper timer operation if ex - ecuted as a single timer control register byte write in - struction. when the timer/event counter is read, the clock is blocked to avoid errors. as this may results in a counting error, blocking of the clock should be taken into account by the programmer. it is strongly recommended to load a desired value into the tmr0/tmr1/tmr2 registers first, before turning on the related timer/event counter, for proper operation since the initial value of the tmr0/tmr1/tmr2 regis - ters are unknown. due to the timer/event counter scheme, the programmer should pay special attention to the instruction to enable then disable the timer for the first time, whenever there is a need to use the timer/event counter function, to avoid unpredictable re - sult. after this procedure, the timer/event counter func - tion can be operated normally. ( ( ( ( ( ( ( ( ( 4 * ) & * 4 7 9 * 4 7 9 * ! " ' 3 ' ( . ( ( < 0 ? = * * < 6 ? = ) * ( / / / * 0 9 , 4 * * , 4 - ' 4 c * * % c * , $ , ' ' 5 & * , $ % c * , $ 0 9 , * / - * 2 ( timer/event counter 0 ( ( 4 * ) & * 4 ' 3 / ' 0 9 , 4 * * , 4 - ' 4 c * * % c * , $ , ' ' 5 & * , $ % c * , $ 0 9 , * / - * 2 ! " 6 0 7 5 8 timer/event counter 1 ht46ru66/ht46cu66 rev. 1.30 21 may 25, 2011 ( ( 4 * ) & * 4 7 9 * 4 7 9 * ! " ' 3 ' . ( < / . / 7 = 7 9 , * / - * 4 * 7 9 , * / - * < = * , 4 - ' 4 c * timer/event counter 2 ! " 2 2 * < = # * * % 2 ( 2 g pfd source option the bit0~bit2 of the tmr0c/tmr2c (t0psc2~0/ t2psc2~0) can be used to define the pre-scaling stages of the inter - nal clock sources of the timer/event counter. the overflow signal of the timer/event counter can be used to generate the pfd signal. the timer prescaler is also used as the pwm counter. bit no. label function 0 1 2 t0psc0 t0psc1 t0psc2 defines the prescaler stages, t0psc2, t0psc1, t0psc0= 000: f int =f sys 001: f int =f sys /2 010: f int =f sys /4 011: f int =f sys /8 100: f int =f sys /16 101: f int =f sys /32 110: f int =f sys /64 111: f int =f sys /128 3 t0e defines the tmr0 active edge of the timer/event counter: in event counter mode (t0m1,t0m0)=(0,1): 1:count on falling edge; 0:count on rising edge in pulse width measurement mode (t0m1,t0m0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge 4 t0on enables/disables the timer counting (0=disable; 1=enable) 5 unused bit, read as 0 6 7 t0m0 t0m1 defines the operating mode, t0m1, t0m0: 01=event count mode (external clock) 10=timer mode (internal clock) 11=pulse width measurement mode 00=unused tmr0c (0eh) register ht46ru66/ht46cu66 rev. 1.30 22 may 25, 2011 bit no. label function 0~2 unused bit, read as 0 3 t1e defines the tmr1 active edge of the timer/event counter: in event counter mode (t1m1,t1m0)=(0,1): 1:count on falling edge; 0:count on rising edge in pulse width measurement mode (t1m1,t1m0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge 4 t1on enables/disables the timer counting (0=disable; 1=enable) 5 t1s defines the tmr1 internal clock source. (0=f sys /4; 1=32768hz) 6 7 t1m0 t1m1 defines the operating mode, t1m1, t1m0: 01=event count mode (external clock) 10=timer mode (internal clock) 11=pulse width measurement mode 00=unused tmr1c (11h) register bit no. label function 0 1 2 t2psc0 t2psc1 t2psc2 defines the prescaler stages, t2psc2, t2psc1, t2psc0= 000: f int =f sys 001: f int =f sys /2 010: f int =f sys /4 011: f int =f sys /8 100: f int =f sys /16 101: f int =f sys /32 110: f int =f sys /64 111: f int =f sys /128 3 t2e defines the tmr2 active edge of the timer/event counter: in event counter mode (t2m1,t2m0)=(0,1): 1:count on falling edge; 0:count on rising edge in pulse width measurement mode (t2m1,t2m0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge 4 t2on enables/disables the timer counting (0=disable; 1=enable) 5 unused bit, read as 0 6 7 t2m0 t2m1 defines the operating mode, t2m1, t2m0: 01=event count mode (external clock) 10=timer mode (internal clock) 11=pulse width measurement mode 00=unused tmr2c (2eh) register ht46ru66/ht46cu66 rev. 1.30 23 may 25, 2011 input/output ports there are 32 bidirectional input/output lines in the device, labeled as pa, pb, pc and pd, which are mapped to the data memory of [12h], [14h], [16h] and [18h] respec - tively. all of these i/o ports can be used for input and out - put operations. for input operation, these ports are non-latching, that is, the inputs must be ready at the t2 rising edge of instruction mov a,[m] (m=12h, 14h, 16h or 18h). for output operation, all the data is latched and remains unchanged until the output latch is rewritten. each i/o line has its own control register (pac, pbc, pcc, pdc) to control the input/output configuration. with this control register, a cmos output or a schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically under software control. to function as an input, the corresponding latch of the control register must be setup as a 1 . the input source also depends on the control register. if the control regis - ter bit is 1 , the input will read the pad state. if the con - trol register bit is 0 , the contents of the latches will move to the internal bus. the latter is possible in the read-modify-write instruction. for an output function, cmos is the only configuration. these control registers are mapped to locations 13h, 15h, 17h and 19h. after a device reset, these i/o lines will default to an input state and will be either high or floating, depending upon the pull-high configuration options. each bit of these in- put/output latches can be set or cleared by the set [m].i and clr [m].i bit manipulation instructions. some instructions first input data and then follow the out - put operations. for example, set [m].i , clr [m].i , cpl [m] , cpla [m] read the entire port states into the cpu, execute the defined bit operations, and then write the results back to the latches or the accumulator. each line of port a has the capability of waking-up the device. each i/o port has a pull-high option. once the pull-high option is selected, the i/o port has a pull-high resistor, otherwise, there s none. take note that a non-pull-high i/o port operating in input mode will cause a floating state. pa0, pa1, pa3, pd4, pd5, pd6 and pd7 are pin-shared with bz, bz , pfd, int0 , int1 , tmr0 and tmr1 pins re - spectively. the pc0, pc6 and pc7 pins are pin-shared with tmr2, tx and rx. pa0 and pa1 are pin-shared with the bz and bz signals, respectively. if the bz/bz option is selected, the output signal in output mode of pa0/pa1 will be the buzzer sig - nal generated by the multi-function timer. the input mode always remain in its original functions. once the bz/bz option is selected, the buzzer output signals are controlled by the pa0 data register only. the i/o func- tions of pa0/pa1 are shown below. pac register pac0 pac register pac1 pa data register pa0 pa data register pa1 output function 0 0 1 x pa0=bz, pa1=bz 0 0 0 x pa0=0, pa1=0 0 1 1 x pa0=bz, pa1=input 0 1 0 x pa0=0, pa1=input 1 0 1 x pa0=input, pa1=bz 1 0 0 x pa0=input, pa1=0 1 1 x x pa0=input, pa1=input note: x stands for don t care d stands for data 0 or 1 pa3 is pin-shared with the signal. if the pfd option is selected and if pa3 is setup as an output, then the output signal on the pa3 pin will be the pfd signal, generated by the timer/event counter overflow signal. if setup as an input it will function as a normal input pin. once the pfd option is selected, the pfd output signal is controlled by the pa3 data reg - ister only. writing a 1 to the pa3 data register will enable the pfd output function while writing a 0 will force the pa3 pin to remain at 0 . the i/o functions of pa3 are shown below. i/o mode i/p (normal) o/p (normal) i/p (pfd) o/p (pfd) pa3 logical input logical output logical input pfd (timer on) note: the pfd frequency is the timer/event counter overflow frequency divided by 2. ht46ru66/ht46cu66 rev. 1.30 24 may 25, 2011 ! " ! " ( * ' * * 4 $ * ' * 1 * 4 $ ( * ' * 0 * 4 $ * ' * 6 * 4 $ $ * ) @ 9 < # * 4 $ = * * # ( / # / # / ( / / / 4 * , * , ) * 4 * & * * 4 * ) * * * , # ( / , : # / , : # # / 2 # . # 6 , ( / # ( . , 6 / # 6 ( / . 1 ( / ) ( / ) / ) / ) / ( 1 / 0 / ( 6 / , : / , : / 2 / ) ( / ) / ) / ) 4 4 9 & & ) @ 9 * g + g g + g input/output ports port pb can also be used as a/d converter inputs. there is a pwm function shared with pd0/pd1/pd2/pd3. if the pwm function is enabled, the pwm0/pwm1/pwm2/ pwm3 signal will appear on pd0/pd1/pd2/pd3, if pd0/ pd1/ pd2/pd3 are operating in output mode. writing 1 to the pd0~pd3 data register will enable the pwm output function while writing 0 will force the pd0~pd3 to remain at 0 . the i/o functions of the pd0/pd1/pd2/pd3 are shown below. i/o mode i/p (normal) o/p (normal) i/p (pwm) o/p (pwm) pd0~pd3 logical input logical output logical input pwm0~pwm3 it is recommended that unused or not bonded out i/o lines should be set as output pins by software instruction to avoid consuming power under input floating state. the definitions of the pfd control signal and pfd output frequency are listed in the following table. timer timer preload value pa3 data register pa3 pad state pfd frequency o f fx00x off x 1 u x on n 0 0 x on n 1 pfd f tmr /[2(m-n)] note: x stands for unused u stands for unknown m is 65536 for pfd0 or pfd1 n is the preload value for the timer/event counter f tmr is input clock frequency for timer/event counter ht46ru66/ht46cu66 rev. 1.30 25 may 25, 2011 ! " * * g + g + 4 * , 4 4 9 & & * , ) * 4 * & * * 4 * ) * * * , 6 / " g * ! # * " g pc7/rx input/output ports ! " ! " * * 4 * , * , ) * 4 * & * * 4 * ) * * * , 0 / " 2 * ! # * " ! # * h * " 4 4 9 & & g + g g + g pc6/tx input/output ports pulse width modulator each devices is provided with either three or four pulse width modulation (pwm) outputs, depending upon which package type is selected. useful for such applica - tions such as motor speed control, the pwm function provides outputs with a fixed frequency but with a duty cycle that can be varied by setting particular values into the corresponding pwm register. a single register, located in the data memory is as - signed to each pwm output. for devices with three pwm outputs, these registers are known as pwm0, pwm1 and pwm2. devices with four pwm outputs re - quire a further additional register known as pwm3. it is here that the 8-bit value, which represents the overall duty cycle of one modulation cycle of the output wave - form, should be placed. to increase the pwm modula - tion frequency, each modulation cycle is subdivided into two or four individual modulation subsections, known as the 7+1 mode or 6+2 mode respectively. the device can choose which mode to use by selecting the appropriate configuration option. when a mode configuration option is chosen, it applies to all pwm outputs on that device. note that when using the pwm, it is only necessary to write the required value into the appropriate pwm regis - ter and select the required mode configuration option, the subdivision of the waveform into its sub-modulation cycles is done automatically within the microcontroller hardware. ht46ru66/ht46cu66 rev. 1.30 26 may 25, 2011 for all devices, the pwm clock source is the system clock f sys . package channels pwm mode output pin pwm register name 52/56-pin 3 6+2 or 7+1 pd0/pd1/pd2 pwm0/pwm1/pwm2 100-pin 4 6+2 or 7+1 pd0/pd1/pd2/pd3 pwm0/pwm1/pwm2/pwm3 pwm function table this method of dividing the original modulation cycle into a further 2 or 4 sub-cycles enable the generation of higher pwm frequencies which allow a wider range of applications to be served. as long as the periods of the generated pwm pulses are less than the time constants of the load, the pwm output will be suitable as such long time constant loads will average out the pulses of the pwm output. the difference between what is known as the pwm cycle frequency and the pwm modulation fre - quency should be understood. as the pwm clock is the system clock, f sys , and as the pwm value is 8-bits wide, the overall pwm cycle frequency is f sys /256. however, when in the 7+1 mode of operation the pwm modulation frequency will be f sys /128, while the pwm modulation frequency for the 6+2 mode of operation will be f sys /64. pwm modulation frequency pwm cycle frequency pwm cycle duty f sys /64 for (6+2) bits mode f sys /128 for (7+1) bits mode f sys /256 [pwm]/256 6+2 pwm mode each full pwm cycle, as it is controlled by an 8-bit pwm register, has 256 clock periods. however, in the 6+2 pwm mode, each pwm cycle is subdivided into four individual sub-cycles known as modulation cycle 0 ~ modulation cycle 3, denoted as i in the table. each one of these four sub-cycles contains 64 clock cycles. in this mode, a modulation frequency increase of four is achieved. the 8-bit pwm register value, which represents the overall duty cycle of the pwm waveform, is divided into two groups. the first group which consists of bit2~bit7 is denoted here as the dc value. the second group which consists of bit0~bit1 is known as the ac value. in the 6+2 pwm mode, the duty cycle value of each of the four modulation sub-cycles is shown in the following table. parameter ac (0~3) duty cycle modulation cycle i (i=0~3) i * * d * 0 / ' 3 4 * $ 4 * 4 * $ 4 * 4 * $ 4 * 4 * $ 4 * ( 6+2 pwm mode & ' ! $ " ( # ' ) b 6 b ( # * * - 4 * - 4 pwm register for 6+2 mode ht46ru66/ht46cu66 rev. 1.30 27 may 25, 2011 7+1 pwm mode each full pwm cycle, as it is controlled by an 8-bit pwm register, has 256 clock periods. however, in the 7+1 pwm mode, each pwm cycle is subdivided into two individual sub-cycles known as modulation cycle 0 ~ modulation cycle 1, denoted as i in the table. each one of these two sub-cycles contains 128 clock cycles. in this mode, a modulation frequency increase of two is achieved. the 8-bit pwm register value, which repre - sents the overall duty cycle of the pwm waveform, is divided into two groups. the first group which consists of bit1~bit7 is denoted here as the dc value. the sec - ond group which consists of bit0 is known as the ac value. in the 7+1 pwm mode, the duty cycle value of each of the two modulation sub-cycles is shown in the following table. parameter ac (0~1) duty cycle modulation cycle i (i=0~1) i * $ 4 * ( ) * $ 4 * d * 1 0 / ' 3 4 * $ 4 * 4 * $ 4 * ( (7+1) pwm mode & ' ! $ " * ( # ' ) b 6 b ( # * * - 4 * - 4 pwm register for 7+1 mode pwm output control on all devices, the pwm outputs are pin-shared with the port d i/o pins. to operate as pwm outputs and not as i/o pins, the correct pwm configuration options must be selected. a 0 must also be written to the cor - responding bits in the i/o port control register pdc to ensure that the required pwm output pins are setup as outputs. after these two initial steps have been carried out, and of course after the required pwm value has been written into the pwm register, writing a 1 to the corresponding bit in the pd output data register will en - able the pwm data to appear on the pin. writing a 0 to the corresponding bit in the pd output data register will disable the pwm output function and force the out - put low. in this way, the port d data output register can be used as an on/off control for the pwm function. note that if the configuration options have selected the pwm function, but a 1 has been written to its corresponding bit in the pdc control register to configure the pin as an input, then the pin can still function as a normal input line, with pull-high resistor options. ht46ru66/ht46cu66 rev. 1.30 28 may 25, 2011 the following sample program shows how the pwm outputs are setup and controlled, the corresponding pwm out - put configuration option must first be selected. clr pdc.0 ; set pin pd0 as output clr pdc.1 ; set pin pd1 as output clr pdc.2 ; set pin pd2 as output clr pdc.3 ; set pin pd3 as output set pd.0 ; pd.0=1; enable pin pd0/pwm0 to be the pwm channel 0 mov a,64h ; pwm0=100d=64h mov pwm0,a set pd.1 ; pd.1=1; enable pin pd1/pwm1 to be the pwm channel 1 mov a,65h ; pwm1=101d=65h mov pwm1,a set pd.2 ; pd.2=1; enable pin pd2/pwm2 to be the pwm channel 2 mov a,66h ; pwm2=102d=66h mov pwm2,a set pd.3 ; pd.3=1; enable pin pd3/pwm3 to be the pwm channel 3 mov a,67h ; pwm3=103d=67h mov pwm3,a clr pd.0 ; disable pwm0 output pd.0 will remain low clr pd.1 ; disable pwm1 output pd.1 will remain low clr pd.2 ; disable pwm2 output pd.2 will remain low clr pd.3 ; disable pwm3 output pd.3 will remain low a/d converter an eight channel and 12 bits resolution a/d converter is implemented in the microcontroller. the reference volt- age is vdd. the a/d converter contains four special registers which are; adrl (24h), adrh (25h), adcr (26h) and acsr (27h). the adrh and adrl registers are the a/d result register higher-order byte and lower-order byte and are read-only. after the a/d con - version is completed, the adrh and adrl should be read to get the conversion result data. the adcr is an a/d converter control register, which defines the a/d channel number, analog channel select, start a/d con - version control bit and the end of a/d conversion flag. to start an a/d conversion, the pb configuration must first be defined, the analog channel selected, after which the start bit can supply a rising and falling edge (0 1 0). at the end of a/d conversion, the eocb bit is cleared. the acsr register is the a/d clock setting reg - ister, which is used to select the a/d clock source. the a/d converter control register is used to control the a/d converter. bit2~bit0 are used to select an analog in - put channel. there are a total of eight channels to se - lect. bit5~bit3 of the adcr are used to set the pb configurations. pb can be an analog input or setup as a normal i/o line, the selected function is determined by these 3 bits. once a pb line is selected as an analog in - put, the i/o function and pull-high resistor of this i/o line are disabled and the a/d converter circuit is pow- ered-on. the eocb bit, bit6 of the adcr is end of a/d conversion flag. this bit can be monitored to know when the a/d conversion has completed. the start bit in the adcr register is used to start the conversion pro- cess of the a/d converter. giving the start bit a rising edge and falling edge means that the a/d conversion has started. in order to ensure that the a/d conversion is completed, the start bit should remain at 0 until the eocb flag is cleared to 0 which indicates the end of the a/d conversion. bit 7 of the acsr register is used for test purposes only and must not be used for other purposes by the applica - tion program. bit1 and bit0 of the acsr register are used to select the a/d clock source. the eocb bit is set to 1 when the start bit is set from 0 to 1. important note for a/d initialisation: special care must be taken to initialise the a/d con - verter each time the port b a/d channel selection bits are modified, otherwise the eocb flag may be in an un - defined condition. an a/d initialisation is implemented by setting the start bit high and then clearing it to zero within 10 instruction cycles of the port b channel selec - tion bits being modified. note that if the port b channel selection bits are all cleared to zero then an a/d initialis - ation is not required. ht46ru66/ht46cu66 rev. 1.30 29 may 25, 2011 bit no. label function 0 1 adcs0 adcs1 selects the a/d converter clock source 00=system clock/2 01=system clock/8 10=system clock/32 11=undefined 2~6 unused bit, read as 0 7 test for test mode used only acsr (27h) register bit no. label function 0 1 2 acs0 acs1 acs2 acs2, acs1, acs0: select a/d channel 0, 0, 0: an0 0, 0, 1: an1 0, 1, 0: an2 0, 1, 1: an3 1, 0, 0: an4 1, 0, 1: an5 1, 1, 0: an6 1, 1, 1: an7 3 4 5 pcr0 pcr1 pcr2 defines the port b configuration select. if pcr0, pcr1 and pcr2 are all zero, the adc circuit is powered off to reduce power consumption. 6 eocb indicates end of a/d conversion. (0 = end of a/d conversion) each time bits 3~5 change state the a/d should be initialised by issuing a start signal, other - wise the eocb flag may have an undefined condition. see important note for a/d initialisation. 7 start starts the a/d conversion. (0 1 0= start; 0 1= reset a/d converter and set eocb to 1) adcr (26h) register pcr2 pcr1 pcr0 76543210 0 0 0 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 0 0 1 pb7 pb6 pb5 pb4 pb3 pb2 pb1 an0 0 1 0 pb7 pb6 pb5 pb4 pb3 pb2 an1 an0 0 1 1 pb7 pb6 pb5 pb4 pb3 an2 an1 an0 1 0 0 pb7 pb6 pb5 pb4 an3 an2 an1 an0 1 0 1 pb7 pb6 pb5 an4 an3 an2 an1 an0 1 1 0 pb7 pb6 an5 an4 an3 an2 an1 an0 1 1 1 an7 an6 an5 an4 an3 an2 an1 an0 port b configuration register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 adrl d3 d2 d1 d0 adrh d11 d10 d9 d8 d7 d6 d5 d4 note: d0~d11 is a/d conversion result data bit lsb~msb. adrl (24h), adrh (25h) register ht46ru66/ht46cu66 rev. 1.30 30 may 25, 2011 the following programming example illustrates how to setup and implement an a/d conversion. the method of polling the eocb bit in the adcr register is used to detect when the conversion cycle is complete. example: using eocb polling method to detect end of conversion mov a,00000001b mov acsr,a ; setup the acsr register to select f sys /8 as the a/d clock mov a,00100000b ; setup adcr register to configure port pb0~pb3 as a/d inputs mov adcr,a ; and select an0 to be connected to the a/d converter : : ; as the port b channel bits have changed the following start ; signal (0-1-0) must be issued within 10 instruction cycles : start_conversion: clr start set start ; reset a/d clr start ; start a/d polling_eoc: sz eocb ; poll the adcr register eocb bit to detect end of a/d conversion jmp polling_eoc ; continue polling mov a,adrh ; read conversion result high byte value from the adrh register mov adrh_buffer,a ; save result to user defined memory mov a,adrl ; read conversion result low byte value from the adrl register mov adrl_buffer,a ; save result to user defined memory : : jmp start_conversion ; start next a/d conversion # # / * - * # # / * - * # # / * - * ( ( ( , ( ( ( , ( ( , ( ( , # , . ( # . # ( c 9 * ' * # / - d * ' * , * ' d * 4 * 4 * & 4 # / * 4 @ * * b * ' 3 / f * ' 3 / 7 * * ' 3 / # k # # k 7 ( # d * * ' * # / - * # / - # / * 4 * * * # * ( ( , ( ( ( , * ' * # / - * # / - ( ( ( , a * , * * * * / a * # / * - * * c * ' ' * * * * * * c * ( , ( ( , * ' * # / - * # / - l * * ' * # / - * ' * # / - * * * $ 4 * f * > * * * $ 4 * 4 4 c # / * 4 * * * # * # / * 4 * * * # * a/d conversion timing ht46ru66/ht46cu66 rev. 1.30 31 may 25, 2011 lcd memory the device provides an area of embedded data memory for lcd display. this area is located from 40h to 6eh of the ram at bank 1. bank pointer (bp; located at 04h of the ram) is the switch between the ram and the lcd display memory. when the bp is set as 1 , any data written into 40h~6eh will affect the lcd display. when the bp is cleared to 0, 2 or 3 , any data written into 40h~6eh is map into the general purpose data mem - ory. the lcd display memory can be read and written to only by indirect addressing mode using mp1. when data is written into the display data area, it is automati - cally read by the lcd driver which then generates the corresponding lcd driving signals. to turn the display on or off, a 1 or a 0 is written to the corresponding bit of the display memory, respectively. the figure illus - trates the mapping between the display memory and lcd pattern for the device. lcd driver output the output number of the device lcd driver can be 47 2 or 47 3or46 4 by option (i.e., 1 / 2 duty, 1 / 3 duty or 1 / 4 duty). the bias type lcd driver can be r type or c type. if the r bias type is selected, no external capaci - tor is required. if the c bias type is selected, a capaci - tor mounted between c1 and c2 pins is needed. the lcd driver bias voltage can be 1 / 2 bias or 1 / 3 bias by option. if 1 / 2 bias is selected, a capacitor mounted be - tween v2 pin and ground is required. if 1 / 3 bias is se - lected, two capacitors are needed for v1 and v2 pins. refer to application diagram. lcd segments as logical output the seg0~seg23 also can be optioned as logical output, once an lcd segment is optioned as a logical output, the contents of bit0 of the related segment address in the lcd ram will appear on the segment. seg0~seg7 are all byte optioned as logical outputs, seg8~seg15 are also byte optioned as logical outputs, seg16~seg23 are individually bit optioned as logical outputs. lcd type r type c type lcd bias type 1 / 2 bias 1 / 3 bias 1 / 2 bias 1 / 3 bias v max if v dd >v lcd , then v max connect to v dd, else v max connect to v lcd if v dd > 3 2 v lcd , then v max connect to v dd , else v max connect to v1 ( 5 ( 5 5 5 0 5 0 5 0 5 , ( ( 1 0 display memory ht46ru66/ht46cu66 rev. 1.30 32 may 25, 2011 ( f * f * + , - ! ' ) . ! $ , $ ( f f * % * / * * % * * % * / * * % * * # 4 4 * * % * - * * ( * * / ' ) % * / * * % * * % * / * * % * * % * / * * % * * % * / * * % * * % * / * * % * * % * / * * % * * % * / * * % * * % * / * * % * * % * / * * % * * % * / * * % * * % * / * * % * * % * / * * % * * % / * * % * * d * e e * * * & * * 4 f * ' * & * / * $ * % * * a % * * * ( f f * * * * 4 & * 4 $ * % * * * * ( * * * 4 & * 4 $ * % * * * * * * * 4 & 4 $ * % * * * * * * * 4 & % * * ( f * * * 4 & * % * * * * ( f * * * * 4 & * % * * f * * * * 4 & * % * * * ( f f * * * * 4 & * # 4 4 * 4 * - * lcd driver output (1 / 3 duty, 1 / 2 byte, r/c type) ht46ru66/ht46cu66 rev. 1.30 33 may 25, 2011 ( * * * * % * * * * 4 & # * , # * , # * , # * , # * , d * / * $ f * / * b f * * $ d * e # e * / * % f * e , e * % f * e e * / * % / * $ f * / * b f * * $ d * e # e * % f * e , e * / * % f * e e * / * % lcd driver output ht46ru66/ht46cu66 rev. 1.30 34 may 25, 2011 low voltage reset/detector functions there is a low voltage detector (lvd) and a low voltage reset circuit (lvr) implemented in this microcontroller. these two functions can be enabled/disabled by options. once the lvd option is enabled, the user can use the rtcc.3 to en - able/disable (1/0) the lvd circuit and read the lvd detector status (0/1) from rtcc.5, otherwise, the lvd function is disabled. the rtcc register definitions are listed below. bit no. label function 0~2 rt0~rt2 8 to 1 multiplexer control inputs to select the real clock prescaler output 3 lvdc* lvd enable/disable (1/0) 4 qosc 32768hz osc quick start-up oscillating 0/1: quick/slow start 5 lvdo lvd detection output (1/0) 1: low voltage detected, read only 6, 7 unused bit, read as 0 note: * once the lvd function is enabled the reference generator should be enabled; otherwise the reference gen - erator is controlled by lvr rom code option. the relationship between lvr and lvd options and lvdc are as shown. rtcc (09h) register the lvr has the same effect or function with the exter - nal res signal which performs a chip reset. during halt state, both lvr and lvd are disabled. the lvr state requires the following specifications: the low voltage (0.9v~v lvr ) has to be maintained for more than 1ms, otherwise, the circuits remain in their original state. if the low voltage state does not exceed 1ms, the lvr will ignore it and do not perform a reset function. the lvr uses the or function with the external res signal to perform a chip reset. the relationship between v dd and v lvr is shown below. note: v opr is the voltage range for proper chip operation at 4mhz system clock. 1 a 1 a ( a ( a ; % 1 a 1 1 a 1 % ( a ; ( * 4 m m 4 * % * * 4 low voltage reset note: *1: to make sure that the system oscillator has stabilized, the sst provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: since low voltage state has to be maintained in its original state for over 1ms, therefore after 1ms delay, the device enters the reset mode. ht46ru66/ht46cu66 rev. 1.30 35 may 25, 2011 uart bus serial interface the ht46ru66/ht46cu66 devices contain an inte - grated full-duplex asynchronous serial communications uart interface that enables communication with exter - nal devices that contain a serial interface. the uart function has many features and can transmit and re - ceive data serially by transferring a frame of data with eight or nine data bits per transmission as well as being able to detect errors when the data is overwritten or in - correctly framed. the uart function possesses its own internal interrupt which can be used to indicate when a reception occurs or when a transmission terminates. uart features the integrated uart function contains the following features: full-duplex, asynchronous communication 8 or 9 bits character length even, odd or no parity options one or two stop bits baud rate generator with 8-bit prescaler parity, framing, noise and overrun error detection support for interrupt on address detect (last character bit=1) separately enabled transmitter and receiver 2-byte deep fifo receive data buffer transmit and receive interrupts interrupts can be initialized by the following conditions: transmitter empty transmitter idle receiver full receiver overrun address mode detect uart external pin interfacing to communicate with an external serial interface, the internal uart has two external pins known as tx and rx. the tx pin is the uart transmitter pin, which can be used as a general purpose i/o pin if the pin is not configured as a uart transmitter, which occurs when the txen bit in the ucr2 control register is equal to zero. similarly, the rx pin is the uart receiver pin, which can also be used as a general purpose i/o pin, if the pin is not configured as a receiver, which occurs if the rxen bit in the ucr2 register is equal to zero. along with the uarten bit, the txen and rxen bits, if set, will automatically setup these i/o pins to their re - spective tx output and rx input conditions and dis - able any pull-high resistor option which may exist on the rx pin. uart data transfer scheme the block diagram shows the overall data transfer structure arrangement for the uart. the actual data to be transmitted from the mcu is first transferred to the txr register by the application program. the data will then be transferred to the transmit shift register from where it will be shifted out, lsb first, onto the tx pin at a rate controlled by the baud rate generator. only the txr register is mapped onto the mcu data memory, the transmit shift register is not mapped and is therefore inaccessible to the application pro - gram. data to be received by the uart is accepted on the external rx pin, from where it is shifted in, lsb first, to the receiver shift register at a rate controlled by the baud rate generator. when the shift register is full, the data will then be transferred from the shift register to the internal rxr register, where it is buffered and can be manipulated by the application program. only the rxr register is mapped onto the mcu data mem - ory, the receiver shift register is not mapped and is therefore inaccessible to the application program. it should be noted that the actual register for data transmission and reception, although referred to in the text, and in application programs, as separate txr and rxr registers, only exists as a single shared reg- ister in the data memory. this shared register known as the txr/rxr register is used for both data trans- mission and data reception. uart status and control registers there are five control registers associated with the uart function. the usr, ucr1 and ucr2 registers control the overall function of the uart, while the brg register controls the baud rate. the actual data to be transmitted and received on the serial interface is managed through the txr/rxr data registers. " * " * , % , * * & ' * * " * , % , - * * & ' * * " * , * % + % + , ' ' ! * * , uart data transfer scheme ht46ru66/ht46cu66 rev. 1.30 36 may 25, 2011 usr register the usr register is the status register for the uart, which can be read by the program to determine the present status of the uart. all flags within the usr register are read only. further explanation on each of the flags is given below: txif the txif flag is the transmit data register empty flag. when this read only flag is 0 it indicates that the character is not transferred to the transmit shift registers. when the flag is 1 it indicates that the transmit shift register has received a character from the txr data register. the txif flag is cleared by reading the uart status register (usr) with txif set and then writing to the txr data register. note that when the txen bit is set, the txif flag bit will also be set since the transmit buffer is not yet full. tidle the tidle flag is known as the transmission com - plete flag. when this read only flag is 0 it indicates that a transmission is in progress. this flag will be set to 1 when the txif flag is 1 and when there is no transmit data, or break character being trans - mitted. when tidle is 1 the tx pin becomes idle. the tidle flag is cleared by reading the usr regis - ter with tidle set and then writing to the txr regis - ter. the flag is not generated when a data character, or a break is queued and ready to be sent. rxif the rxif flag is the receive register status flag. when this read only flag is 0 it indicates that the rxr read data register is empty. when the flag is 1 it indicates that the rxr read data register con- tains new data. when the contents of the shift regis- ter are transferred to the rxr register, an interrupt is generated if rie=1 in the ucr2 register. if one or more errors are detected in the received word, the appropriate receive-related flags nf, ferr, and/or perr are set within the same clock cycle. the rxif flag is cleared when the usr register is read with rxif set, followed by a read from the rxr reg - ister, and if the rxr register has no data available. ridle the ridle flag is the receiver status flag. when this read only flag is 0 it indicates that the receiver is between the initial detection of the start bit and the completion of the stop bit. when the flag is 1 it in - dicates that the receiver is idle. between the com - pletion of the stop bit and the detection of the next start bit, the ridle bit is 1 indicating that the uart is idle. oerr the oerr flag is the overrun error flag, which indi - cates when the receiver buffer has overflowed. when this read only flag is 0 there is no overrun er - ror. when the flag is 1 an overrun error occurs which will inhibit further transfers to the rxr receive data register. the flag is cleared by a software se - quence, which is a read to the status register usr followed by an access to the rxr data register. ferr the ferr flag is the framing error flag. when this read only flag is 0 it indicates no framing error. when the flag is 1 it indicates that a framing error has been detected for the current character. the flag can also be cleared by a software sequence which will involve a read to the usr status register followed by an access to the rxr data register. nf the nf flag is the noise flag. when this read only flag is 0 it indicates a no noise condition. when the flag is 1 it indicates that the uart has de- tected noise on the receiver input. the nf flag is set during the same cycle as the rxif flag but will not be set in the case of an overrun. the nf flag can be cleared by a software sequence which will involve a read to the usr status register, followed by an ac - cess to the rxr data register. ! $ b 6 % 2 b ( " 2 % " 2 * * * $ d * & * ' * * * & ' * * * * * ( d * & * * ' * * * & ' * * 4 d * * * * ( d * * * - * " * * d * " * * & * - 4 b 4 * ( d * " * * * $ - * d * - * * 4 ( d * * b * - - * d * - * * ( d * * - * * 2 * * ' 4 d * ' * * ( d * * ' * * ' 4 d * * ( d * * * $ * * ' 4 d * $ * * ( d * * $ * * 2 ht46ru66/ht46cu66 rev. 1.30 37 may 25, 2011 perr the perr flag is the parity error flag. when this read only flag is 0 it indicates that a parity error has not been detected. when the flag is 1 it indi - cates that the parity of the received word is incor - rect. this error flag is applicable only if parity mode (odd or even) is selected. the flag can also be cleared by a software sequence which involves a read to the usr status register, followed by an ac - cess to the rxr data register. ucr1 register the ucr1 register together with the ucr2 register are the two uart control registers that are used to set the various options for the uart function, such as overall on/off control, parity control, data transfer bit length etc. further explanation on each of the bits is given below: tx8 this bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the transmitted data, known as tx8. the bno bit is used to determine whether data transfers are in 8-bit or 9-bit format. rx8 this bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the received data, known as rx8. the bno bit is used to determine whether data transfers are in 8-bit or 9-bit format. txbrk the txbrk bit is the transmit break character bit. when this bit is 0 there are no break characters and the tx pin operates normally. when the bit is 1 there are transmit break characters and the transmitter will send logic zeros. when equal to 1 after the buffered data has been transmitted, the transmitter output is held low for a minimum of a 13-bit length and until the txbrk bit is reset. stops this bit determines if one or two stop bits are to be used. when this bit is equal to 1 two stop bits are used, if the bit is equal to 0 then only one stop bit is used. prt this is the parity type selection bit. when this bit is equal to 1 odd parity will be selected, if the bit is equal to 0 then even parity will be selected. pren this is parity enable bit. when this bit is equal to 1 the parity function will be enabled, if the bit is equal to 0 then the parity function will be disabled. bno this bit is used to select the data length format, which can have a choice of either 8-bits or 9-bits. if this bit is equal to 1 then a 9-bit data length will be selected, if the bit is equal to 0 then an 8-bit data length will be selected. if 9-bit data length is se - lected then bits rx8 and tx8 will be used to store the 9th bit of the received and transmitted data re - spectively. uarten the uarten bit is the uart enable bit. when the bit is 0 the uart will be disabled and the rx and tx pins will function as general purpose i/o pins. when the bit is 1 the uart will be enabled and the tx and rx pins will function as defined by the txen and rxen control bits. when the uart is disabled it will empty the buffer so any character re- maining in the buffer will be discarded. in addition, the baud rate counter value will be reset. when the uart is disabled, all error and status flags will be reset. the txen, rxen, txbrk, rxif, oerr, ferr, perr, and nf bits will be cleared, while the tidle, txif and ridle bits will be set. other con- trol bits in ucr1, ucr2, and brg registers will re- main unaffected. if the uart is active and the uarten bit is cleared, all pending transmissions and receptions will be terminated and the module will be reset as defined above. when the uart is re-enabled it will restart in the same configuration. ! $ b 6 , ! # b ( " , + " 7 " 7 * * b * 7 * < c * 4 $ = - * * b * 7 * < * 4 $ = * b @ * & d * * b @ * & ( d * * b @ * & ' * & * b * ' * * b d * c * * b ( d * * * b $ * $ * b d * * $ * ' * $ * ( d * - * $ * ' * $ * $ * b 4 * b d * $ * ' * b 4 ( d * $ * ' * b 4 b * ' * * ' * b d * ; 9 b * * ' ( d * 7 9 b * * ' ! # * b 4 * b d * b 4 * ! # f * " * h * " * * * ! # * ( d * b 4 * ! # f * " * h * " * * * / * * ht46ru66/ht46cu66 rev. 1.30 38 may 25, 2011 ! $ b 6 ) # + # " " b ( * $ * * b 4 d * " 2 * * n * b 4 ( d * " 2 * * n * b 4 * 4 * * b 4 d * % * * n * b 4 ( d * % * * n * b 4 - * * b 4 d * " 2 * * n * b 4 ( d * " 2 * * n * b 4 ' * & * " * c @ * * b 4 d * " * c @ * * b 4 * < ' 4 4 * = ( d * " * c @ * * b 4 # * * d * b 4 ( d * b 4 5 & * b * * 4 * b d * & & * ( d * 4 c * - * b 4 * b d * - * b 4 ( d * - * b 4 * b 4 * b d * * b 4 ( d * * b 4 , 5 ucr2 register the ucr2 register is the second of the two uart control registers and serves several purposes. one of its main functions is to control the basic enable/dis - able operation of the uart transmitter and receiver as well as enabling the various uart interrupt sources. the register also serves to control the baud rate speed, receiver wake-up enable and the address detect enable. further explanation on each of the bits is given below: teie this bit enables or disables the transmitter empty interrupt. if this bit is equal to 1 when the transmit - ter empty txif flag is set, due to a transmitter empty condition, the uart interrupt request flag will be set. if this bit is equal to 0 the uart inter - rupt request flag will not be influenced by the condi - tion of the txif flag. tiie this bit enables or disables the transmitter idle in - terrupt. if this bit is equal to 1 when the transmitter idle tidle flag is set, the uart interrupt request flag will be set. if this bit is equal to 0 the uart in - terrupt request flag will not be influenced by the condition of the tidle flag. rie this bit enables or disables the receiver interrupt. if this bit is equal to 1 when the receiver overrun oerr flag or receive data available rxif flag is set, the uart interrupt request flag will be set. if this bit is equal to 0 the uart interrupt will not be influenced by the condition of the oerr or rxif flags. wake this bit enables or disables the receiver wake-up function. if this bit is equal to 1 and if the mcu is in the power down mode, a low going edge on the rx input pin will wake-up the device. if this bit is equal to 0 and if the mcu is in the power down mode, any edge transitions on the rx pin will not wake-up the device. adden the adden bit is the address detect mode bit. when this bit is 1 the address detect mode is en - abled. when this occurs, if the 8th bit, which corre - sponds to rx7 if bno=0, or the 9th bit, which corresponds to rx8 if bno=1, has a value of 1 then the received word will be identified as an ad - dress, rather than data. if the corresponding inter - rupt is enabled, an interrupt request will be generated each time the received word has the ad - dress bit set, which is the 8 or 9 bit depending on the value of bno. if the address bit is 0 an interrupt will not be generated, and the received data will be discarded. brgh the brgh bit selects the high or low speed mode of the baud rate generator. this bit, together with the value placed in the brg register, controls the baud rate of the uart. if this bit is equal to 1 the high speed mode is selected. if the bit is equal to 0 the low speed mode is selected. rxen the rxen bit is the receiver enable bit. when this bit is equal to 0 the receiver will be disabled with any pending data receptions being aborted. in addi- tion the buffer will be reset. in this situation the rx pin can be used as a general purpose i/o pin. if the rxen bit is equal to 1 the receiver will be enabled and if the uarten bit is equal to 1 the rx pin will be controlled by the uart. clearing the rxen bit during a transmission will cause the data reception to be aborted and will reset the receiver. if this oc- curs, the rx pin can be used as a general purpose i/o pin. ht46ru66/ht46cu66 rev. 1.30 39 may 25, 2011 txen the txen bit is the transmitter enable bit. when this bit is equal to 0 the transmitter will be disabled with any pending transmissions being aborted. in addition the buffer will be reset. in this situation the tx pin can be used as a general purpose i/o pin. if the txen bit is equal to 1 the transmitter will be enabled and if the uarten bit is equal to 1 the tx pin will be controlled by the uart. clearing the txen bit during a transmission will cause the trans - mission to be aborted and will reset the transmitter. if this occurs, the tx pin can be used as a general purpose i/o pin. baud rate generator to setup the speed of the serial data communication, the uart function contains its own dedicated baud rate generator. the baud rate is controlled by its own internal free running 8-bit timer, the period of which is determined by two factors. the first of these is the value placed in the brg register and the second is the value of the brgh bit within the ucr2 control regis - ter. the brgh bit decides, if the baud rate generator is to be used in a high speed mode or low speed mode, which in turn determines the formula that is used to calculate the baud rate. the value in the brg register determines the division factor, n, which is used in the following baud rate calculation formula. note that n is the decimal value placed in the brg register and has a range of between 0 and 255. ucr2 brgh bit 0 1 baud rate f [64 (n + 1)] sys f [16 (n + 1)] sys by programming the brgh bit which allows selection of the related formula and programming the required value in the brg register, the required baud rate can be setup. note that because the actual baud rate is determined using a discrete value, n, placed in the brg register, there will be an error associated be - tween the actual and requested value. the following example shows how the brg register value n and the error value can be calculated. calculating the register and error values for a clock frequency of 8mhz, and with brgh set to 0 determine the brg register value n, the actual baud rate and the error value for a desired baud rate of 9600. from the above table the desired baud rate br f [64 (n + 1)] sys re-arranging this equation gives n f (brx64) sys 1 giving a value for n 8000000 9600 64 () x 1 12.0208 to obtain the closest value, a decimal value of 12 should be placed into the brg register. this gives an actual or calculated baud rate value of br 8000000 [64(12 + 1)] 9615 therefore the error is equal to = 0.16% ; 0 1 * ; 0 ( ( ; 0 ( ( the following tables show actual values of baud rate and error values for the two values of brgh. baud rate k/bps baud rates for brgh=0 f sys =8mhz f sys =7.159mhz f sys =4mhz f sys =3.579545mhz brg kbaud error brg kbaud error brg kbaud error brg kbaud error 0.3 207 0.300 0.00 185 0.300 0.00 1.2 103 1.202 0.16 92 1.203 0.23 51 1.202 0.16 46 1.19 -0.83 2.4 51 2.404 0.16 46 2.38 -0.83 25 2.404 0.16 22 2.432 1.32 4.8 25 4.807 0.16 22 4.863 1.32 12 4.808 0.16 11 4.661 -2.9 9.6 12 9.615 0.16 11 9.322 -2.9 6 8.929 -6.99 5 9.321 -2.9 19.2 6 17.857 -6.99 5 18.64 -2.9 2 20.83 8.51 2 18.643 -2.9 38.4 2 41.667 8.51 2 37.29 -2.9 1 1 57.6 1 62.5 8.51 1 55.93 -2.9 0 62.5 8.51 0 55.93 -2.9 115.2 0 125 8.51 0 111.86 -2.9 baud rates and error values for brgh 0 ht46ru66/ht46cu66 rev. 1.30 40 may 25, 2011 baud rate k/bps baud rates for brgh=1 f sys =8mhz f sys =7.159mhz f sys =4mhz f sys =3.579545mhz brg kbaud error brg kbaud error brg kbaud error brg kbaud error 0.3 1.2 207 1.202 0.16 185 1.203 0.23 2.4 207 2.404 0.16 185 2.405 0.23 103 2.404 0.16 92 2.406 0.23 4.8 103 4.808 0.16 92 4.811 0.23 51 4.808 0.16 46 4.76 -0.83 9.6 51 9.615 0.16 46 9.520 -0.832 25 9.615 0.16 22 9.727 1.32 19.2 25 19.231 0.16 22 19.454 1.32 12 19.231 0.16 11 18.643 -2.9 38.4 12 38.462 0.16 11 37.287 -2.9 6 35.714 -6.99 5 37.286 -2.9 57.6 8 55.556 -3.55 7 55.93 -2.9 3 62.5 8.51 3 55.930 -2.9 115.2 3 125 8.51 3 111.86 -2.9 1 125 8.51 1 111.86 -2.9 250 1 250 0 0 250 0 baud rates and error values for brgh 1 setting up and controlling the uart introduction for data transfer, the uart function utilizes a non-return-to-zero, more commonly known as nrz, format. this is composed of one start bit, eight or nine data bits, and one or two stop bits. parity is supported by the uart hardware, and can be setup to be even, odd or no parity. for the most common data format, 8 data bits along with no par- ity and one stop bit, denoted as 8, n, 1, is used as the default setting, which is the setting at power-on. the number of data bits and stop bits, along with the parity, are setup by programming the corresponding bno, prt, pren, and stops bits in the ucr1 register. the baud rate used to transmit and receive data is setup using the internal 8-bit baud rate gen - erator, while the data is transmitted and received lsb first. although the uart s transmitter and re - ceiver are functionally independent, they both use the same data format and baud rate. in all cases stop bits will be used for data transmission. enabling/disabling the uart the basic on/off function of the internal uart func - tion is controlled using the uarten bit in the ucr1 register. as the uart transmit and receive pins, tx and rx respectively, are pin-shared with normal i/o pins, one of the basic functions of the uarten con - trol bit is to control the uart function of these two pins. if the uarten, txen and rxen bits are set, then these two i/o pins will be setup as a tx output pin and an rx input pin respectively, in effect dis - abling the normal i/o pin function. if no data is being transmitted on the tx pin then it will default to a logic high value. clearing the uarten bit will disable the tx and rx pins and allow these two pins to be used as normal i/o pins. when the uart function is disabled the buffer will be reset to an empty condition, at the same time discarding any remaining residual data. disabling the uart will also reset the error and sta - tus flags with bits txen, rxen, txbrk, rxif, oerr, ferr, perr and nf being cleared while bits tidle, txif and ridle will be set. the re- maining control bits in the ucr1, ucr2 and brg registers will remain unaffected. if the uarten bit in the ucr1 register is cleared while the uart is active, then all pending transmissions and recep- tions will be immediately suspended and the uart will be reset to a condition as defined above. if the uart is then subsequently re-enabled, it will restart again in the same configuration. data, parity and stop bit selection the format of the data to be transferred, is com - posed of various factors such as data bit length, parity on/off, parity type, address bits and the num - ber of stop bits. these factors are determined by the setup of various bits within the ucr1 register. the bno bit controls the number of data bits which can be set to either 8 or 9, the prt bit controls the choice of odd or even parity, the pren bit controls the parity on/off function and the stops bit decides whether one or two stop bits are to be used. the fol - lowing table shows various formats for data trans - mission. the address bit identifies the frame as an address character. the number of stop bits, which can be either one or two, is independent of the data length. ht46ru66/ht46cu66 rev. 1.30 41 may 25, 2011 start bit data bits address bits parity bits stop bit example of 8-bit data formats 18001 17011 171 1 01 example of 9-bit data formats 19001 18011 181 1 01 transmitter receiver data format the following diagram shows the transmit and receive waveforms for both 8-bit and 9-bit data formats. uart transmitter data word lengths of either 8 or 9 bits, can be selected by programming the bno bit in the ucr1 register. when bno bit is set, the word length will be set to 9 bits. in this case the 9th bit, which is the msb, needs to be stored in the tx8 bit in the ucr1 register. at the transmitter core lies the transmitter shift register, more commonly known as the tsr, whose data is ob - tained from the transmit data register, which is known as the txr register. the data to be transmitted is loaded into this txr register by the application pro- gram. the tsr register is not written to with new data until the stop bit from the previous transmission has been sent out. as soon as this stop bit has been trans- mitted, the tsr can then be loaded with new data from the txr register, if it is available. it should be noted that the tsr register, unlike many other regis- ters, is not directly mapped into the data memory area and as such is not available to the application program for direct read/write operations. an actual transmis- sion of data will normally be enabled when the txen bit is set, but the data will not be transmitted until the txr register has been loaded with data and the baud rate generator has defined a shift clock source. how - ever, the transmission can also be initiated by first loading data into the txr register, after which the txen bit can be set. when a transmission of data be - gins, the tsr is normally empty, in which case a transfer to the txr register will result in an immediate transfer to the tsr. if during a transmission the txen bit is cleared, the transmission will immediately cease and the transmitter will be reset. the tx output pin will then return to having a normal general purpose i/o pin function. transmitting data when the uart is transmitting data, the data is shifted on the tx pin from the shift register, with the least significant bit first. in the transmit mode, the txr register forms a buffer between the internal bus and the transmitter shift register. it should be noted that if 9-bit data format has been selected, then the msb will be taken from the tx8 bit in the ucr1 register. the steps to initiate a data transfer can be summarized as follows: make the correct selection of the bno, prt, pren and stops bits to define the required word length, parity type and number of stop bits. setup the brg register to select the desired baud rate. set the txen bit to ensure that the tx pin is used as a uart transmitter pin and not as an i/o pin. access the usr register and write the data that is to be transmitted into the txr register. note that this step will clear the txif bit. this sequence of events can now be repeated to send additional data. it should be noted that when txif=0, data will be in - hibited from being written to the txr register. clear - ing the txif flag is always achieved using the following software sequence: 1. a usr register access 2. a txr register write execution the read-only txif flag is set by the uart hard- ware and if set indicates that the txr register is empty and that other data can now be written into the txr register without overwriting the previous data. if the teie bit is set then the txif flag will gen- erate an interrupt. during a data transmission, a write instruction to the txr register will place the data into the txr regis- ter, which will be copied to the shift register at the end of the present transmission. when there is no data transmission in progress, a write instruction to the txr register will place the data directly into the shift register, resulting in the commencement of data transmission, and the txif bit being immedi - ately set. when a frame transmission is complete, which happens after stop bits are sent or after the break frame, the tidle bit will be set. to clear the tidle bit the following software sequence is used: 1. a usr register access 2. a txr register write execution note that both the txif and tidle bits are cleared by the same software sequence. * , , * ( , * , * , * , * , * 1 , * 0 , * 6 * , > , $ * , 0 ! . * , , * ( , * , * , * , * , * 1 , * 0 , * 6 * , > , $ * , 1 ! . , * 7 ht46ru66/ht46cu66 rev. 1.30 42 may 25, 2011 transmit break if the txbrk bit is set then break characters will be sent on the next transmission. break character transmission consists of a start bit, followed by 13 n 0 bits and stop bits, where n=1, 2, etc. if a break character is to be transmitted then the txbrk bit must be first set by the application program, then cleared to generate the stop bits. transmitting a break character will not generate a transmit inter - rupt. note that a break condition length is at least 13 bits long. if the txbrk bit is continually kept at a logic high level then the transmitter circuitry will transmit continuous break characters. after the ap - plication program has cleared the txbrk bit, the transmitter will finish transmitting the last break character and subsequently send out one or two stop bits. the automatic logic highs at the end of the last break character will ensure that the start bit of the next frame is recognized. uart receiver introduction the uart is capable of receiving word lengths of ei - ther 8 or 9 bits. if the bno bit is set, the word length will be set to 9 bits with the msb being stored in the rx8 bit of the ucr1 register. at the receiver core lies the receive serial shift register, commonly known as the rsr. the data which is received on the rx external input pin, is sent to the data recovery block. the data recovery block operating speed is 16 times that of the baud rate, while the main receive serial shifter operates at the baud rate. after the rx pin is sampled for the stop bit, the received data in rsr is transferred to the receive data register, if the register is empty. the data which is received on the external rx input pin is sampled three times by a majority de- tect circuit to determine the logic level that has been placed onto the rx pin. it should be noted that the rsr register, unlike many other registers, is not di - rectly mapped into the data memory area and as such is not available to the application program for direct read/write operations. receiving data when the uart receiver is receiving data, the data is serially shifted in on the external rx input pin, lsb first. in the read mode, the rxr register forms a buffer between the internal bus and the receiver shift register. the rxr register is a two byte deep fifo data buffer, where two bytes can be held in the fifo while a third byte can continue to be received. note that the application program must ensure that the data is read from rxr before the third byte has been completely shifted in, otherwise this third byte will be discarded and an overrun error oerr will be subsequently indicated. the steps to initiate a data transfer can be summarized as follows: make the correct selection of bno, prt, pren and stops bits to define the word length, parity type and number of stop bits. setup the brg register to select the desired baud rate. set the rxen bit to ensure that the rx pin is used as a uart receiver pin and not as an i/o pin. at this point the receiver will be enabled which will begin to look for a start bit. when a character is received the following se - quence of events will occur: the rxif bit in the usr register will be set when rxr register has data available, at least one more character can be read. when the contents of the shift register have been transferred to the rxr register, then if the rie bit is set, an interrupt will be generated. if during reception, a frame error, noise error, par - ity error, or an overrun error has been detected, then the error flags can be set. the rxif bit can be cleared using the following software sequence: 1. a usr register access 2. an rxr register read execution receive break any break character received by the uart will be managed as a framing error. the receiver will count and expect a certain number of bit times as speci - fied by the values programmed into the bno and stops bits. if the break is much longer than 13 bit times, the reception will be considered as complete after the number of bit times specified by bno and stops. the rxif bit is set, ferr is set, zeros are loaded into the receive data register, interrupts are generated if appropriate and the ridle bit is set. if a long break signal has been detected and the re- ceiver has received a start bit, the data bits and the invalid stop bit, which sets the ferr flag, the re- ceiver must wait for a valid stop bit before looking for the next start bit. the receiver will not make the assumption that the break condition on the line is the next start bit. a break is regarded as a character that contains only zeros with the ferr flag set. the break character will be loaded into the buffer and no further data will be received until stop bits are re - ceived. it should be noted that the ridle read only flag will go high when the stop bits have not yet been received. the reception of a break character on the uart registers will result in the following: the framing error flag, ferr, will be set. the receive data register, rxr, will be cleared. the oerr, nf, perr, ridle or rxif flags will possibly be set. idle status when the receiver is reading data, which means it will be in between the detection of a start bit and the reading of a stop bit, the receiver status flag in the usr register, otherwise known as the ridle flag, will have a zero value. in between the reception of a stop bit and the detection of the next start bit, the ridle flag will have a high value, which indicates the receiver is in an idle condition. ht46ru66/ht46cu66 rev. 1.30 43 may 25, 2011 receiver interrupt the read only receive interrupt flag rxif in the usr register is set by an edge generated by the receiver. an interrupt is generated if rie=1, when a word is transferred from the receive shift register, rsr, to the receive data register, rxr. an overrun error can also generate an interrupt if rie=1. managing receiver errors several types of reception errors can occur within the uart module, the following section describes the various types and how they are managed by the uart. overrun error - oerr flag the rxr register is composed of a two byte deep fifo data buffer, where two bytes can be held in the fifo register, while a third byte can continue to be received. before this third byte has been entirely shifted in, the data should be read from the rxr register. if this is not done, the overrun error flag oerr will be consequently indicated. in the event of an overrun error occurring, the fol - lowing will happen: the oerr flag in the usr register will be set. the rxr contents will not be lost. the shift register will be overwritten. an interrupt will be generated if the rie bit is set. the oerr flag can be cleared by an access to the usr register followed by a read to the rxr register. noise error - nf flag over-sampling is used for data recovery to identify valid incoming data and noise. if noise is detected within a frame the following will occur: the read only noise flag, nf, in the usr register will be set on the rising edge of the rxif bit. data will be transferred from the shift register to the rxr register. no interrupt will be generated. however this bit rises at the same time as the rxif bit which itself generates an interrupt. note that the nf flag is reset by a usr register read operation followed by an rxr register read operation. framing error - ferr flag the read only framing error flag, ferr, in the usr register, is set if a zero is detected instead of stop bits. if two stop bits are selected, both stop bits must be high, otherwise the ferr flag will be set. the ferr flag is buffered along with the received data and is cleared on any reset. parity error - perr flag the read only parity error flag, perr, in the usr register, is set if the parity of the received word is in - correct. this error flag is only applicable if the parity is enabled, pren = 1, and if the parity type, odd or even is selected. the read only perr flag is buf - fered along with the received data bytes. it is cleared on any reset. it should be noted that the ferr and perr flags are buffered along with the corresponding word and should be read before reading the data word. uart interrupt scheme the uart internal function possesses its own inter - nal interrupt and independent interrupt vector. several individual uart conditions can generate an internal uart interrupt. these conditions are, a transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect and an rx pin wake-up. when any of these conditions are cre- ated, if the uart interrupt is enabled and the stack is not full, the program will jump to the uart interrupt vector where it can be serviced before returning to the main program. four of these conditions, have a corre- sponding usr register flag, which will generate a uart interrupt if its associated interrupt enable flag in ! * * $ 2 4 * " 2 * 4 2 4 * % - * # - 4 b 4 * " 2 - * - 2 4 * " 6 * ' * , k ( " 7 * ' * , k # ( ( " * ) @ 9 ) # + ( ! * ! # * n * 2 4 ! 2 ! ( ! * ( ( ( uart interrupt scheme ht46ru66/ht46cu66 rev. 1.30 44 may 25, 2011 the ucr2 register is set. the two transmitter interrupt conditions have their own corresponding enable bits, while the two receiver interrupt conditions have a shared enable bit. these enable bits can be used to mask out individual uart interrupt sources. the address detect condition, which is also a uart interrupt source, does not have an associated flag, but will generate a uart interrupt when an address detect condition occurs if its function is enabled by setting the adden bit in the ucr2 register. an rx pin wake-up, which is also a uart interrupt source, does not have an associated flag, but will generate a uart interrupt if the microcontroller is woken up by a low go - ing edge on the rx pin, if the wake and rie bits in the ucr2 register are set. note that in the event of an rx wake-up interrupt occurring, there will be a delay of 1024 system clock cycles before the system re - sumes normal operation. note that the usr register flags are read only and cannot be cleared or set by the application program, neither will they be cleared when the program jumps to the corresponding interrupt servicing routine, as is the case for some of the other interrupts. the flags will be cleared automatically when certain actions are taken by the uart, the details of which are given in the uart register section. the overall uart interrupt can be disabled or enabled by the euri bit in the intc1 interrupt control register to prevent a uart in - terrupt from occurring. address detect mode setting the address detect mode bit, adden, in the ucr2 register, enables this special mode. if this bit is enabled then an additional qualifier will be placed on the generation of a receiver data available interrupt, which is requested by the rxif flag. if the adden bit is enabled, then when data is available, an interrupt will only be generated, if the highest received bit has a high value. note that the euri and emi interrupt en- able bits must also be enabled for correct interrupt generation. this highest address bit is the 9th bit if bno=1 or the 8th bit if bno=0. if this bit is high, then the received word will be defined as an address rather than data. a data available interrupt will be generated every time the last bit of the received word is set. if the adden bit is not enabled, then a receiver data avail - able interrupt will be generated each time the rxif flag is set, irrespective of the data last bit status. the address detect mode and parity enable are mutually exclusive functions. therefore if the address detect mode is enabled, then to ensure correct operation, the parity function should be disabled by resetting the par - ity enable bit to zero. adden bit 9 if bno=1, bit 8 if bno=0 uart interrupt generated 0 0 1 1 0x 1 adden bit function uart operation in power down mode when the mcu is in the power down mode the uart will cease to function. when the device enters the power down mode, all clock sources to the module are shutdown. if the mcu enters the power down mode while a transmission is still in progress, then the transmission will be terminated and the external tx transmit pin will be forced to a logic high level. in a similar way, if the mcu enters the power down mode while receiving data, then the reception of data will likewise be terminated. when the mcu enters the power down mode, note that the usr, ucr1, ucr2, transmit and receive registers, as well as the brg register will not be affected. the uart function contains a receiver rx pin wake-up function, which is enabled or disabled by the wake bit in the ucr2 register. if this bit, along with the uart enable bit, uarten, the receiver enable bit, rxen and the receiver interrupt bit, rie, are all set before the mcu enters the power down mode, then a falling edge on the rx pin will wake-up the mcu from the power down mode. note that as it takes 1024 system clock cycles after a wake-up, be- fore normal microcontroller operation resumes, any data received during this time on the rx pin will be ig- nored. for a uart wake-up interrupt to occur, in addition to the bits for the wake-up being set, the global interrupt enable bit, emi, and the uart interrupt enable bit, euri must also be set. if these two bits are not set then only a wake up event will occur and no interrupt will be generated. note also that as it takes 1024 sys - tem clock cycles after a wake-up before normal microcontroller resumes, the uart interrupt will not be generated until after this time has elapsed. options the following shows the options in the device. all these options should be defined in order to ensure having a proper functioning system. options osc type selection. this option is to determine if an rc or crystal or 32768hz crystal oscillator is chosen as system clock. wdt, rtc and time base clock source selection. there are three types of selections: system clock/4 or rtc osc or wdt osc. ht46ru66/ht46cu66 rev. 1.30 45 may 25, 2011 options wdt enable/disable selection. wdt can be enabled or disabled by option. wdt time-out period selection. there are four types of selection: wdt clock source divided by 2 12 /f s ~2 13 /f s ,2 13 /f s ~2 14 /f s ,2 14 /f s ~2 15 /f s or 2 15 /f s ~2 16 /f s . clr wdt times selection. this option defines the method to clear the wdt by instruction. one time means that the clr wdt can clear the wdt. two times means only if both of the clr wdt1 and clr wdt2 have been executed, only then can the wdt be cleared. time base time-out period selection. the time base time-out period ranges from clock/2 12 to clock/2 15 . clock means the clock source selected by options. buzzer output frequency selection. there are eight types of frequency signals for the buzzer output: clock/2 2 ~ clock/2 9 . clock means the clock source selected by options. wake-up selection. this option defines the wake-up capability. external i/o pins (pa only) all have the capability to wake-up the chip from a halt by a falling edge (bit option). pull-high selection. this option is to determine whether the pull-high resistance is viable or not in the input mode of the i/o ports. pa, pb, pc and pd can be independently selected (bit option). i/o pins share with other function selections. pa0/bz , pa1/bz: pa0 and pa1 can be set as i/o pins or buzzer outputs. pa3/pfd: pa3 can be set as i/o pins or pfd output. lcd common selection. there are three types of selections: 2 common (1 / 2 duty) or 3 common (1 / 3 duty) or 4 common (1 / 4 duty). if the 4 common is selected, the segment output pin seg46 will be set as a common output. lcd bias power supply selection. there are two types of selections: 1 / 2 bias or 1 / 3 bias lcd bias type selection. this option is to determine what kind of bias is selected, r type or c type (low or high bias current option). lcd driver clock frequency selection. there are seven types of frequency signals for the lcd driver circuits: f s /2 2 ~f s /2 8 . f s stands for the clock source se - lection by options. lcd on/off at halt selection. lcd segments as logical output selection, (byte, byte, bit, bit, bit, bit, bit, bit, bit, bit option) [seg0~seg7], [seg8~seg15], seg16, seg17, seg18, seg19, seg20, seg21, seg22, or seg23 lvr selection. lvr has enable or disable options lvd selection. lvd has enable or disable options pfd selection. if pa3 is set as pfd output, there are two types of selections; one is pfd0 as the pfd output, the other is pfd1 as the pfd output. pfd0, pfd1 are the timer overflow signals of the timer/event counter 0, timer/event counter 1 re - spectively. pwm selection: (7+1) or (6+2) mode pd0: level output or pwm0 output pd1: level output or pwm1 output pd2: level output or pwm2 output pd3: level output or pwm3 output int0 or int1 triggering edge selection: disable; high to low; low to high; low to high or high to low. application circuits note: 1. crystal/resonator system oscillators for crystal oscillators, c1 and c2 are only required for some crystal frequencies to ensure oscillation. for resonator applications c1 and c2 are normally required for oscillation to occur. for most applications it is not necessary to add r1. however if the lvr function is disabled, and if it is required to stop the oscillator when vdd falls below its operating range, it is recommended that r1 is added. the values of c1 and c2 should be selected in consultation with the crystal/resonator manufacturer specifications. 2. reset circuit the reset circuit resistance and capacitance values should be chosen to ensure that vdd is stable and re - mains within its operating voltage range before the res pin reaches a high level. ensure that the length of the wiring connected to the res pin is kept as short as possible, to avoid noise interference. 3. for applications where noise may interfere with the reset circuit and for details on the oscillator external com - ponents, refer to application note ha0075e for more information. ht46ru66/ht46cu66 rev. 1.30 46 may 25, 2011 ( . / 0 ( . 1 % 4 % * c * 4 $ % ( a 2 ( a 2 ( a 2 6 0 7 5 8 # " 0 / ( 6 / / ( 1 / # ( / , : # / , : # # / 2 # . # 6 . , ( / # ( , 6 / # 6 ( / ) ( / ) . ! % ! 2 $ $ % ! , , @ o o ' 3 / 6 ( 2 3 * 0 4 2 $ , 2 $ $ % ! , , * * * 4 ' % * 5 & * 4 . 1 ( / 0 / " 6 / " 2 $ , $ 2 $ $ % ! , , 2 * f * f * * * ( a 2 ( ( @ ( a 2 $ ! % ! ht46ru66/ht46cu66 rev. 1.30 47 may 25, 2011 instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of pro - gram instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of pro - gramming overheads. for easier understanding of the various instruction codes, they have been subdivided into several func - tional groupings. instruction timing most instructions are implemented within one instruc - tion cycle. the exceptions to this are branch, call, or ta - ble read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5 s and branch or call instructions would be im - plemented within 1 s. although instructions which re - quire one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instruc- tions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to imple- ment. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instruc- tions would be clr pcl or mov pcl, a . for the case of skip instructions, it must be noted that if the re- sult of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specific imme - diate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to en - sure correct handling of carry and borrow data when re - sults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on pro - gram requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specified locations using the jmp instruction or to a sub- routine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the sub - routine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made re - garding the condition of a certain data memory or indi - vidual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the pro - gram perhaps determined by the condition of certain in - put switches or by the condition of internal data bits. ht46ru66/ht46cu66 rev. 1.30 48 may 25, 2011 bit operations the ability to provide single bit operations on data mem - ory is an extremely flexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the fea - ture removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write pro - cess is taken care of automatically when these bit oper - ation instructions are used. table read operations data storage is normally implemented by using regis - ters. however, when working with large amounts of fixed data, the volume involved often makes it inconve - nient to store the fixed data in the data memory. to over - come this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instruc - tions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt in - struction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electro - magnetic environments. for their relevant operations, refer to the functional related sections. instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be con - sulted as a basic instruction reference using the follow - ing listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from the acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry, result in data memory decimal adjust acc for addition with result in data memory 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] logical and data memory to acc logical or data memory to acc logical xor data memory to acc logical and acc to data memory logical or acc to data memory logical xor acc to data memory logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 note 1 note 1 note 1 1 1 1 note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 note 1 1 note z z z z ht46ru66/ht46cu66 rev. 1.30 49 may 25, 2011 mnemonic description cycles flag affected rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read table (current page) to tblh and data memory read table (last page) to tblh and data memory 2 note 2 note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to, pdf to, pdf to, pdf none none to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the to and pdf flags remain unchanged. instruction definition adc a,[m] add data memory to acc with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the accumulator. operation acc acc+[m]+c affected flag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the specified data memory. operation [m] acc+[m]+c affected flag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected flag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specified immediate data are added. the result is stored in the accumulator. operation acc acc+x affected flag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the specified data memory. operation [m] acc + [m] affected flag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) z andm a,[m] logical and acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) z ht46ru66/ht46cu66 rev. 1.30 50 may 25, 2011 call addr subroutine call description unconditionally calls a subroutine at the specified address. the program counter then in - crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruc - tion. operation stack program counter + 1 program counter addr affected flag(s) none clr [m] clear data memory description each bit of the specified data memory is cleared to 0. operation [m] 00h affected flag(s) none clr [m].i clear bit of data memory description bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) none clr wdt clear watchdog timer description the to, pdf flags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc- tion with clr wdt2 and must be executed alternately with clr wdt2 to have effect. re- petitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc - tion with clr wdt1 and must be executed alternately with clr wdt1 to have effect. re - petitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf ht46ru66/ht46cu66 rev. 1.30 51 may 25, 2011 cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. operation [m] [m] affected flag(s) z cpla [m] complement data memory with result in acc description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected flag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd ( binary coded decimal) value re - sulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac flag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c flag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by add - ing 00h, 06h, 60h or 66h depending on the accumulator and flag conditions. only the c flag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected flag(s) c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) z deca [m] decrement data memory with result in acc description data in the specified data memory is decremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. operation to 0 pdf 1 affected flag(s) to, pdf ht46ru66/ht46cu66 rev. 1.30 52 may 25, 2011 inc [m] increment data memory description data in the specified data memory is incremented by 1. operation [m] [m]+1 affected flag(s) z inca [m] increment data memory with result in acc description data in the specified data memory is incremented by 1. the result is stored in the accumu - lator. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected flag(s) none mov a,[m] move data memory to acc description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) none mov a,x move immediate data to acc description the immediate data specified is loaded into the accumulator. operation acc x affected flag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specified data memory. operation [m] acc affected flag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected flag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical or oper - ation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) z ht46ru66/ht46cu66 rev. 1.30 53 may 25, 2011 or a,x logical or immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical or op - eration. the result is stored in the accumulator. operation acc acc or x affected flag(s) z orm a,[m] logical or acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical or oper - ation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the re - stored address. operation program counter stack affected flag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specified immediate data. program execution continues at the restored address. operation program counter stack acc x affected flag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by set- ting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed be- fore returning to the main program. operation program counter stack emi 1 affected flag(s) none rl [m] rotate data memory left description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 affected flag(s) none rla [m] rotate data memory left with result in acc description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory re - main unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 [m].7 affected flag(s) none ht46ru66/ht46cu66 rev. 1.30 54 may 25, 2011 rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 c c [m].7 affected flag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 c c [m].7 affected flag(s) c rr [m] rotate data memory right description the contents of the specified data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 affected flag(s) none rra [m] rotate data memory right with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit with bit 0 ro- tated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 [m].0 affected flag(s) none rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry flag is rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 c c [m].0 affected flag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit. bit 0 re - places the carry bit and the original carry flag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 c c [m].0 affected flag(s) c ht46ru66/ht46cu66 rev. 1.30 55 may 25, 2011 sbc a,[m] subtract data memory from acc with carry description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] c affected flag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the data memory. note that if the re - sult of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] c affected flag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are first decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] 1 skip if [m] = 0 affected flag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specified data memory are first decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] 1 skip if acc = 0 affected flag(s) none set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) none set [m].i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) none ht46ru66/ht46cu66 rev. 1.30 56 may 25, 2011 siz [m] skip if increment data memory is 0 description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m]+1 skip if [m] = 0 affected flag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in - struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m]+1 skip if acc = 0 affected flag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specified data memory is not 0, the following instruction is skipped. as this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected flag(s) none sub a,[m] subtract data memory from acc description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] affected flag(s) ov, z, ac, c subm a,[m] subtract data memory from acc with result in data memory description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] affected flag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specified by the code is subtracted from the contents of the accumu - lator. the result is stored in the accumulator. note that if the result of subtraction is nega - tive, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc x affected flag(s) ov, z, ac, c ht46ru66/ht46cu66 rev. 1.30 57 may 25, 2011 swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specified data memory are interchanged. operation [m].3~[m].0 [m].7 ~ [m].4 affected flag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specified data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3 ~ acc.0 [m].7 ~ [m].4 acc.7 ~ acc.4 [m].3 ~ [m].0 affected flag(s) none sz [m] skip if data memory is 0 description if the contents of the specified data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruc - tion. operation skip if [m] = 0 affected flag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specified data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m] = 0 affected flag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specified data memory is 0, the following instruction is skipped. as this re- quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i = 0 affected flag(s) none tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none ht46ru66/ht46cu66 rev. 1.30 58 may 25, 2011 xor a,[m] logical xor data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical xor op - eration. the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) z xorm a,[m] logical xor acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical xor op - eration. the result is stored in the data memory. operation [m] acc xor [m] affected flag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected flag(s) z ht46ru66/ht46cu66 rev. 1.30 59 may 25, 2011 package information 52-pin qfp (14mm 14mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.681 0.689 b 0.547 0.555 c 0.681 0.689 d 0.547 0.555 e 0.039 f 0.016 g 0.098 0.122 h 0.134 i 0.004 j 0.029 0.041 k 0.004 0.008 07 symbol dimensions in mm min. nom. max. a 17.30 17.50 b 13.90 14.10 c 17.30 17.50 d 13.90 14.10 e 1.00 f 0.40 g 2.50 3.10 h 3.40 i 0.10 j 0.73 1.03 k 0.10 0.20 07 ht46ru66/ht46cu66 rev. 1.30 60 may 25, 2011 ; ( 1 6 # , 0 2 5 p + 56-pin ssop (300mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.395 0.420 b 0.291 0.299 c 0.008 0.012 c 0.720 0.730 d 0.089 0.099 e 0.025 f 0.004 0.010 g 0.025 0.035 h 0.004 0.012 08 symbol dimensions in mm min. nom. max. a 10.03 10.67 b 7.39 7.59 c 0.20 0.30 c 18.29 18.54 d 2.26 2.51 e 0.64 f 0.10 0.25 g 0.64 0.89 h 0.10 0.30 08 ht46ru66/ht46cu66 rev. 1.30 61 may 25, 2011 1 0 # ; 7 , 2 l 5 100-pin lqfp (14mm 14mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.626 0.634 b 0.547 0.555 c 0.626 0.634 d 0.547 0.555 e 0.020 f 0.008 g 0.053 0.057 h 0.063 i 0.004 j 0.018 0.030 k 0.004 0.008 07 symbol dimensions in mm min. nom. max. a 15.90 16.10 b 13.90 14.10 c 15.90 16.10 d 13.90 14.10 e 0.50 f 0.20 g 1.35 1.45 h 1.60 i 0.10 j 0.45 0.75 k 0.10 0.20 07 ht46ru66/ht46cu66 rev. 1.30 62 may 25, 2011 ( ( 1 # , 1 ( 0 2 5 p + 1 6 1 6 0 ht46ru66/ht46cu66 rev. 1.30 63 may 25, 2011 holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales office) 5f, unit a, productivity building, no.5 gaoxin m 2nd road, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538 tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com copyright 2010 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. |
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